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Visitor rajavenk
Visitor
711 Views
Registered: ‎08-04-2014

Readback Verify and Capture on SSI devices

Hi,

I am interested in implementing readback verify and capture using SelectMAP on Virtex 7 series (7V2000T) and Ultrascale (VU440) FPGAs. The configuration users guide for both families (UG470 and UG570) only mention readback command sequence for monolithic FPGAs but have no information on how to do the same for SSI devices with multiple SLRs. Where can i find command sequence for multiple SLR devices?

I looked into the RBA file of a bitstream (ascii file that contains the readback commands) and I notice that the readback is being done 4 times i.e. the monolithic readback sequence described in UG470 is performed 4 times once for each SLR (Virtex-7 2000T FPGA). Each iteration of readback sequence only differs by the IDCODE. So i believe by setting IDCODE values to correct SLR we want to target, we can readback from that corresponding SLR.

My assumption is, in order to do readback verify or capture from different SLRs, we need to write the IDCODE for each individual SLR before performing readback verify or capture using the command sequence described for monolithic dies. Is this correct? Is there anything else to it? Am i missing something?

I have tried to change the IDCODE (which was extracted from the bitstream) for each SLR before performing the readback based on the assumption above but every time i receive the same data i.e.
1. I set Master SLR IDCODE, perform monolithic readback command sequence, store the readback data.
2. Change the IDCODE to one of the Slave SLRs and again perform monolithic readback command sequence and store the data.

Both the data stored in step 1 and 2 above are identical which means the readback is not happening on the slave SLRs. Can someone suggest what i might be missing.

Attached is the command sequence for readback for SSI devices based on my understanding so far. Please go through and suggest if i missed something important.

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2 Replies
Xilinx Employee
Xilinx Employee
603 Views
Registered: ‎06-13-2018

Re: Readback Verify and Capture on SSI devices

Hi @rajavenk,

We are looking into this internally. We will get back to you.

 

Regards,

Priyanka Patil

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Xilinx Employee
Xilinx Employee
519 Views
Registered: ‎01-21-2013

Re: Readback Verify and Capture on SSI devices

Hi @rajavenk, @panantra,

Some good references for Readback for monolithic devices which you are probably already aware of include the below.

UltraScale

7-series

 

We don’t have anything fully documented yet for SSI devices.

However, to address your queries directly.

 

“My assumption is, in order to do readback verify or capture from different SLRs, we need to write the IDCODE for each individual SLR before performing readback verify or capture using the command sequence described for monolithic dies. Is this correct? Is there anything else to it? Am i missing something?”

          There is one IDCODE per device, not per SLR.

          There is not an IDCODE read needed to do any readback even on the master. I’m not sure whether you read some documentation that led you to believe so?

 

“I have tried to change the IDCODE (which was extracted from the bitstream) for each SLR before performing the readback based on the assumption above but every time i receive the same data i.e.
1. I set Master SLR IDCODE, perform monolithic readback command sequence, store the readback data.
2. Change the IDCODE to one of the Slave SLRs and again perform monolithic readback command sequence and store the data.”

          These steps would be incorrect.

          For SSI devices, I would follow the sequence set out in XAPP1230, Table 5, Page 14, for the Master SLR.  

          Then you need to insert a Type2 write 134217727 words to Slave SLR. This command is needed to read the Slave SLR. We will be documenting this in the future.

                    So after the Sync word of the slave SLR sequence, you’d need 0x3003C000 and 0x57FFFFFF.

          I believe a colleague is assisting you with this sequence. Once we have that ironed out, we can post the update on this thread.

Thanks,
Wendy
Xilinx Technical Support
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