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Visitor
Visitor
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Registered: ‎09-22-2014

Relation between CLB count and configuration memory bits

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Hi every body

In a reconfugurable FPGA, is there any relation between the amount of CLB a circuit requires on the FPGA and the ammount of configuration bits on SRAM memory to store the bitstream of the circuit?

Are they two distinct features or they are dependent to each other?

Please clarify me and make some examples.

Thank you.

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Professor
Professor
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Registered: ‎08-14-2007

@venkata wrote:
Bitstream size is not depandent on the design size. You can find the bitstream size of any device in the device specific configuration user guide.

That's mostly true.  However many Xilinx devices have the capability to use compressed bitstreams.  The bitstream data compression method is fairly simple, and does not help for a mostly full part.  However in a design that uses very little of the FPGA inernal resources it can be considerably smaller than the un-compressed bitsteam.

-- Gabor

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Moderator
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Registered: ‎02-16-2010
Bitstream size is not depandent on the design size. You can find the bitstream size of any device in the device specific configuration user guide.
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Professor
Professor
15,255 Views
Registered: ‎08-14-2007

@venkata wrote:
Bitstream size is not depandent on the design size. You can find the bitstream size of any device in the device specific configuration user guide.

That's mostly true.  However many Xilinx devices have the capability to use compressed bitstreams.  The bitstream data compression method is fairly simple, and does not help for a mostly full part.  However in a design that uses very little of the FPGA inernal resources it can be considerably smaller than the un-compressed bitsteam.

-- Gabor

View solution in original post

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Visitor
Visitor
8,531 Views
Registered: ‎09-22-2014
Thank you venkata
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Visitor
Visitor
8,531 Views
Registered: ‎09-22-2014
Thank you
I love those who help others :)
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