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Registered: ‎04-02-2012

Required mcs data format information for FPGA configuration

Hi,

We are using ML605 board and writing .mcs file to external BPI flash using microblaze.So, queries are as follows:

1.need data format information to store .mcs onto BPI flash (means lower byte or higher byte first on flash)

2.How FPGA comes to know, end of configuration data file?during power on configuration

 

Please let me know

Thanks and Regards,

Prashant 

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Scholar
Scholar
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Registered: ‎02-27-2008

Prashant,

 

I suggest you download all the examples, build them, load them, and learn.

 

http://www.xilinx.com/products/boards-and-kits/EK-V6-ML605-G.htm

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎04-02-2012

thanks Austin Lesea,

 

I have downloaded all files but they are not solving our purpose so pls help me

 

Prashant

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Registered: ‎02-27-2008

http://www.xilinx.com/support/documentation/user_guides/ug360.pdf

 

Have you read this guide?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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http://www.fpga-faq.com/archives/33100.html#33108

 

and there is a ton of information on the mcs file format out there....

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Thanks Austin Lesea,

As .mcs frame format file consists of many fields like addr, device ID, data, checksum etc.

Is all these information is written onto BPI flash ,when it is programmed through JTAG? or only data is written because FPGA needs only data.

Pls let me know.

 

Regards,

Prashant

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Registered: ‎02-27-2008

Prashant,


The bitstream sytarts with the sync character string, and ends with the CRC check and startup commands.

 

Everything else before the sync is to document it for you.


Everything after the startup may be required for the startup (there may be a number of empty bytes at the end that need to be sent).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎04-02-2012

Thanks for your reply.

I need to understand the configuration data available for virtex-6 fpga.

The maximum configuration data available for virtex-6 fpga is 74Mbits and in ML605 board, FPGA connected to BPI flash which is 256Mbits of size.So, how fpga get configured, if configuration memory is more than 74Mbits.

 

Thanks and Regards,

Prashant

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Registered: ‎12-14-2011

On this thread, I was hoping someone could help clear up a few unknowns for me.

 

1. The mcs file is in ASCII format. But you have to write the data in hex, right? (For clarity).

2. Which fields from the mcs file get written? At a guess, I would ignore everything except the data. Do I need to grab the payload from the Extended Linear Address field and concatenate it with the Hex address at the start of each Data record to generate my absolute address to write to the PROM at the beginning of each Page Program operation? Of which there would be one per data record?

3. Send all data including the sync sequence, so the FPGA can figure out what's going on as the serial stream arrives.

 

So in conclusion for the following file (snippet) :

:020000040000FA

:10000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00

:10001000AA99556630A10007200031A10628314178

:100020003D00316109EE31C20400809330E100CF20

 

I would actually write the following into my PROM from my processor:

1. PROM instruction : BULK Erase = 0xC7

2. PROM instruction : Write Enable = 0x06

3. PROM instruction : Page Write = 0x02, 0x00 0x0000 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

4. PROM instruction : Page Write = 0x02, 0x00 0x0010 0xAA99556630A10007200031A106283141

5. PROM instruction : Page Write = 0x02, 0x00 0x0020 0x3D00316109EE31C20400809330E100CF ...

 

Above the extended linear address field is 4 hex characters, which with the 16 bit hex address gives a total of 32 address bits. But the device is only 32M, and has 24 address bits. So I have to be careful to throw away unwanted address bits?

 

Hopefully the example above will allow someone who knows what they are looking at to correct my errors. Thanks in advance.

 

Al.

 

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Xilinx Employee
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Registered: ‎09-05-2007

I had to go through this whilst preparing the Flash memory programming reference designs for the Spartan-3 Starter kits. For example this PicoBlaze based design can read an MCS file and program a StartaFlash memory...

 

http://www.xilinx.com/products/boards/s3estarter/files/s3esk_picoblaze_nor_flash_programmer.zip

http://www.xilinx.com/products/boards/s3estarter/files/s3esk_picoblaze_nor_flash_programmer.pdf

 

 

It looks like you are almost there yourself but here are my notes concerning MCS format (that I made at the time) which form the basis of the PicoBlaze code provided in the example indicated above.

 

If the address is less than 32-bits then you just use the lower bits (the upper bits should be zero anyway). The memory is only written with the ‘data’ and everything else defines where it should be written and provides a checksum that you can (should) use to verify that the memory is being programmed correctly (e.g. detect any communication errors). Each ASCII character represents a hexadecimal value and therefore 4-bits so remember to write the actual bits and not the ASCII character (I have truly lost count of how many people have made that mistake and asked me why it doesn’t work!).

 

 

INTEL MCS-86 file format notes.

 

Ken Chapman - 31st October 2005

 

 

Each line has a 9-character prefix with 4 fields

 

:       Start Character

bb      Byte count - number of data bytes on the line e.g. 10 is 16 bytes of data

aaaa    Address

tt      Record type

          00 = Data record

          01 = End of file record

          04 = Extended Linear Address Record - provides offset to be added to the addresses.

 

This is followed by data bytes if relevant and a checksum         

 

dddddd  Data bytes

cc      Checksum for the whole record formed by adding all bytes and 2's complementing the 8-bit result.

 

 

Here are some lines from a programming file for an XC3S500E

 

FIRST LINE

 

:020000040000FA

 

: 02 0000 04    00 00     FA

 

:       Start Character

02      2 data bytes

0000    Address (unused in this record type)

04      Record type 04 (Extended Linear Address Record)

00 00   Offset address (zero in this case to start at address zero)

FA      Checksum 02+00+00+04+00+00 = 06  Complement = FA

 

So after this line the full address is 0000aaaa.

 

 

MOST LINES (first 2 shown)

 

:10000000FFFFFFFF5599AA660C000180000000E089

:100010000C800680000000060C8004800000FCA715

 

 

: 10 0000 00   FF FF FF FF 55 99 AA 66 0C 00 01 80 00 00 00 E0    89

: 10 0010 00   0C 80 06 80 00 00 00 06 0C 80 04 80 00 00 FC A7    15

 

 

:       Start Character

10      16 data bytes

0000

0010    Address increasing by 16 each line given that there are 16 bytes on a line

00      Data record

FF FF FF FF 55 99 AA 66 0C 00 01 80 00 00 00 E0

0C 80 06 80 00 00 00 06 0C 80 04 80 00 00 FC A7

        Byte data (16 bytes on each line)

89

15      Checksum

          Sum of {10 00 00 00 FF FF FF FF 55 99 AA 66 0C 00 01 80 00 00 00 E0} = 777 Complement 77 = 89

          Sum of {10 00 10 00 0C 80 06 80 00 00 00 06 0C 80 04 80 00 00 FC A7} = 3EB Complement EB = 15

 

 

 

 

CROSSING ADDRESS BOUNDARY LINE

 

Because the address field in each data record is only 16-bits, it means that an address can only

be up to FFFF. When the file size is larger than this, it needs to use the Extended Linear Address Record

to specify the next most significant bytes of the address.

 

:10FFF0000000000000000000000000000000000001

:020000040001F9

:1000000000000000000000000000000000000000F0

 

 

: 02 0000 04   00 01   F9

 

:       Start Character

02      2 data bytes

0000    Address (unused in this record type)

04      Record type 04 (Extended Linear Address Record)

00 01   Offset address to be added to address provided with data records

FA      Checksum 02+00+00+04+00+01 = 07  Complement = F9

 

 

So after this line the full address is 0001aaaa

 

 

 

LAST LINE

 

 

:00000001FF

 

: 00 0000 01 FF

 

:       Start Character

00      no data

0000    Address (unused in this record type)

01      End of file record

FF      Checksum 

           Sum of {00 00 00 01} = 01 Complement 01 = FF

 

Ken Chapman
Principal Engineer, Xilinx UK
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Registered: ‎12-14-2011

Thank you, Ken. Great explanation.

Al.
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Registered: ‎08-18-2017

Hi All,

 

Thank you for this information on the mcs file.  Does anyone know how to compute the CRC32 that is at the end of the configuration data?

 

I know the polynomial, but I don't know what byte the CRC starts at, which byte it ends at.

 

I know it is seeded with 0xFFFFFFFF.  Are the input bytes bit flipped in quad spi mode? 

 

A concrete example would be great.  I'm trying to build a quad_spi controller that can also read and compute the CRC32 for verification in system.

 

Keith

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