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Visitor
Visitor
287 Views
Registered: ‎05-25-2020

Reset after partial reconfiguration

Hi, maybe you can help me with PR problem: Im working on kintex 7 fpga. When I am loading my full design everything is Ok. But when the microblaze loading the reconfigurable partition- something bad happens (I can see a different behavior in each version). When I reset the entire system (with sdk)-it seems to be working. 

1. I have tried to use the reset_after_reconfig feature but the microblaze is dying.

2. I have tried to create my own reset with decoupling this partition signals but it doesnt help. 

Any idea?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

It sounds like a design issue - you reset the entire design and it will then work, this means you don't do better decoupling between the static and dynamic. Look into the interface carefully and make sure the PR does not affect the static part, say, hold the interface idle if needed.

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Visitor
Visitor
213 Views
Registered: ‎05-25-2020

thank you for the reply! Im not enabling the dynamic output until it should be stable. I will try to disable it completely and see what happens. 

Any idea about the reset_after_reconfig feature (with snapping mode) that crashes the fpga?

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Visitor
Visitor
189 Views
Registered: ‎05-25-2020

When I run "report drc" I see a message about cells with init value that does not have a reset. But I can see in the schematic that those cells are connected to my reset signal. So why I get this message? Maybe this is related to my problem?

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