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Observer wangxiguang
Observer
541 Views
Registered: ‎08-14-2014

S25FL128S VIO timing requirment

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Hi,

I'm using S25FL128S with VIO=1.8V. I found a "strange" requirement in S25FL128S datasheet, which says:

98ffb44b2552772406d698eb479d16c.png

Apparently, the VIO have to track VCC, which is hard to be satisfied.

I checked schematic of ZC706, and didn't found any special design about VIO-VCC timing and tracking. So I'd like to know, what will happen if VIO doesn't satisfy the requirement of datasheet? Is Xilinx considered this requirement, or just ignored it?

Thanks.

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1 Solution

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Observer wangxiguang
Observer
397 Views
Registered: ‎08-14-2014

Re: S25FL128S VIO timing requirment

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Thanks for reply @iguo and @drjohnsmith .

But I think maybe I mis-described my question, and ZC706 DO use this VIO feature.

I downloaded the latest datasheet of S25FL128S, and the 200mV requirement is no longer exists. 

Now it only requires that VIO is less than VCC, and this is quite easier to meet.

Thanks both of you anyway~

baabfeb35f8c0f589483878bc6b67ba.png

3 Replies
Xilinx Employee
Xilinx Employee
436 Views
Registered: ‎08-10-2008

回复: S25FL128S VIO timing requirment

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Do you need a versatile I/O interface at your design? If not, why just ignore this? Simply connect this pin to Vcc and all will goes well.

I don't think any Xilinx board makes use of this versatile interface as there is no need. SPI<->FPGA usually has a I/O connection at a constant voltage level.

If you have a certain chip and the interface would change voltage levels at a real time, you can use this Vio, then yes, you need to track Vcc during power-up stage. If you cannot satisfy it but you still need to use it, you should consult Cypress about the possible consequences.

 

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Scholar drjohnsmith
Scholar
424 Views
Registered: ‎07-09-2009

Re: S25FL128S VIO timing requirment

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Just to generalise @iguo s very valid response 

A lot of chips have different voltages on the IO pins compared to the core pins,

   including the fpgas

This is to allow the core to run at a optimised frequency, and the IO at the voltage the system you need.

I dont know the board you have, but I'd assume that the core and IO are tied together, so always meet the tracking requirement.

As you highlight, If you do make a design with  different IO voltage to the core, there is quite often a requirement to track both together as the power is turned on, 

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Observer wangxiguang
Observer
398 Views
Registered: ‎08-14-2014

Re: S25FL128S VIO timing requirment

Jump to solution

Thanks for reply @iguo and @drjohnsmith .

But I think maybe I mis-described my question, and ZC706 DO use this VIO feature.

I downloaded the latest datasheet of S25FL128S, and the 200mV requirement is no longer exists. 

Now it only requires that VIO is less than VCC, and this is quite easier to meet.

Thanks both of you anyway~

baabfeb35f8c0f589483878bc6b67ba.png