04-19-2021 07:54 AM - edited 04-20-2021 01:28 AM
After adding the SEM IP module into the design, voltage of SPI clock (custom-made SPI slave IP) swings only between 0.85V and 3.3V and can't reach 0V as shown in the attached picture. When SEM IP is disabled, SPI clock works well and voltage swings between 0V and 3.3V (2nd picture). I would like to know why is SEM IP causing this problem and how to resolve it. SEM IP initializes correctly and we are using Artix-7 100T chip.
P.S. Our hardware engineers checked and verified that there isn't any issue with the PCB trace of SPI clock signal.
04-25-2021 12:33 AM
This is interesting. SEM IP is independent and should has no relationship with other user logic.
How your SPI clock is created and routed? Does its creation and routing have any intereaction with SEM IP? Note that the clock of SEM IP is not recommended to be shared with other logic.
04-26-2021 02:52 AM
Hi iguo and thanks for your reply.
We found what is the problem. Our MCU and FPGA share the same SPI bus, but FPGA is set to Master SPI configuration mode. According to the UG470, FPGA's Master SPI clock is not turned off when SEU detection is used so we have a conflict on the SPI clock line. Is there something we can do in our code to disable FPGA's Master clock when SEU detection is used?