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Registered: ‎01-29-2018

SEM IP core example design

 Hi guys,

I'm working on a custom board with Xilinx xc7z020 fpga and I'd like to add SEM IP core to the existing design for fault injection, in order to evaluate the response of the system.
I saw this video tutorial in which are used 4 signals (clock, uart tx- rx and a gpio to drive clock buffer enable) to interact with a uart2sem rtl module connected to SEM IP core, and I'd like to use this method in my design.


Opening the example design in Vivado 2017.1 I noticed that SEM is not supported in IP integrator, but that's not a problem since I can use "make external" and route the signals in the block design to SEM; I also noticed that the example design is different from the one in the video. It is composed by a top-level entity with sub-entities: sem_0, sem_0_sem_mon and sem_0_sem_cfg.

it seems like that the uart2sem rtl module and the other components used in the video tutorial have been incorporated into the example design. Can anyone confirm it?

I'd like to understand the structure of the example in order to use it in my current design.
The ports of the top level entity are:

- clk

- status signals

- inject_strobe and inject_address

- monitor_tx and monitor_rx.

I suppose monitor_tx and monitor_rx must be connected to uart_rx and uart_tx of the microprocessor, inject_strobe and inject_address can be left unconnected since I want to inject errors through the monitor interface and also status signal, because I can monitor the states of the SEM controller via uart.

Clock input is connected to a buffer and then to a buffer with enable: respect to the example in the video, the top level entity doesn't have a dedicated input port to drive the buffer enable  thrugh a GPIO of the microporcessor, but it's always enabled. 

It is not clear to me why in this example design is not necessary to enable clock via microprocessor gpio.


Does anyone have to share some documentation about how to use the example design in a project (maybe a picture of the block diagram in order to understand the connections) and a SDK code that use uart as interface? I read some documents and application notes but they aren't referred to this example design.
I'm also curious if anyone tried the SDK code in the video tutorial and what I have to change in order to make it compatible with my design.




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3 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-10-2008

Almost every answer is addressed in pg036; and the best way to learn is to generate a example design in Vivado by ourself.
sem_mon is part of the example design, as this example design is the SEU solution Xilinx provides, you need to incorporate the whole example into your design, not the xci file.

Don't forget to reply, kudo, and accept as solution.
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Registered: ‎01-29-2018


Thanks for your reply. As I said, I imported the example design, connected:
-uart_tx to monitor_rx

-uart_rx to monitor_tx

-100 MHz processor clock to input clock

- inject strobe and inject address tied to '0'

- I noticed that in the example design icap_grant is tied to '1', so I left it as it is, whitout using a GPIO.

I also mapped some status signal to the leds of the board to visualize the status of the controller.
I used the sdk code provided in this thread:

which is:


#include <stdio.h>
#include <xil_printf.h>
#include <xil_types.h>
#include "platform.h"
#include "xil_io.h"

int main()
    volatile unsigned int ctrl;
    volatile unsigned int reset;

    xil_printf("Hello World\n\r");

    reset = Xil_In32(0xF8000240);
    xil_printf("RESETS: %08x\n\r",reset);

    Xil_Out32(0xF8000240,0x0000000EU);  // to ensure icap_grant is 0

    ctrl = Xil_In32(0xF8007000);
    xil_printf("PCAP DEVCFG CTRL: %08x\n\r",ctrl);


    ctrl = Xil_In32(0xF8007000);
    xil_printf("ICAP DEVCFG CTRL: %08x\n\r",ctrl);

    xil_printf("ICAP granted\n\r");
    Xil_Out32(0xF8000240,0x0000000CU);  // icap_grant to 1

    reset = Xil_In32(0xF8000240);
    xil_printf("RESETS: %08x\n\r",reset);

    return 0;



I noticed that the controller seems to work, because I can see from the led that initially status initialization is asserted and then status observation, however I can't interact with the controller, since I expect to find this message:

SC 01
FS 02
SC 02


but it is blocked and I can't write characters on the screen.

Anyone has a working SDK code to share? Thanks 


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Registered: ‎01-29-2018

Any help on this one?


I'm a bit confused about what this lines of codes does: from the documentation I understood that bit 27 of XDCFG_CTRL_PCAP_PR
_MASK (PCAP_PR) register must be cleared (address 0xF007000), and then enable icap_grant through a GPIO, but in this case it writes FPGA_RST_CTRL (register 0xF8000240)?

Has anyone managed to make this code work?


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