UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer 400garrison
Observer
467 Views
Registered: ‎04-11-2017

SEM and MultiBoot Implementation

Jump to solution

I am trying to put together a solution which is running Xilinx MultiBoot (golden image and an update image) as well as using the SEM core configured for correction by replacement.

The application of MultiBoot for us is to facilitate firmware upgrades for units that have left the factory and are in the field. For instance, a customer needs a new firmware image in which case we'll send out a support package that in turn overwrites the "update" image stored in off-chip non-volatile.

Here's where I have question: I see in PG036 v4.1 in the Implementation section (page 108) one of the final steps in implementing the core is to write a programming file which should then be written to the SEM's instance of non-volatile.

Does that mean every time I want to use MultiBoot for a firmware-upgrade of the "update image" I also have to JTAG-program the SEM flash?

I am hoping the controller populates the SEM flash by copying the on-chip CRAM automagically while it is in the" initialization" state.

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
374 Views
Registered: ‎06-05-2013

Re: SEM and MultiBoot Implementation

Jump to solution
It seems you are targeting 7 series. You can refer to following XAPP https://www.xilinx.com/support/documentation/application_notes/xapp733-multiboot-sem-controller.pdf

From the above XAPP:

A successful MultiBoot event depends on the next bitstream being properly stored at a known address in a non-volatile device suitably interfaced to the FPGA for configuration. The required amount of storage for FPGA configuration depends on the number of bitstreams to be stored, the bitstream size, and a few second-order considerations described in the FPGA configuration user guides.

Designers might also need to consider the organization of SEM controller data. A SEM controller instance uses external data if one or both of these optional features are enabled:

• Error correction by replace
• Error classification

When these optional features are enabled, the SEM controller example design includes a simplified serial peripheral interface (SPI) master through which the SEM controller accesses data in an SPI flash. The SPI flash is dedicated to the SEM controller and independent from any nonvolatile devices used for FPGA configuration

Thanks
Harshit
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
4 Replies
430 Views
Registered: ‎09-17-2018

Re: SEM and MultiBoot Implementation

Jump to solution

The SEM replacement bitstream must match your .bit bitstream (both generated together).

There is no magic:  you must ensure they match.

l.e.o.

 

399 Views
Registered: ‎01-22-2015

Re: SEM and MultiBoot Implementation

Jump to solution

@400garrison 

     I also have to JTAG-program the SEM flash?
I too am wondering about this.  From reading “External Memory Programming File” on about pae 110 of PG036, it sounds like the tools create a special .mcs file that we must place (ie. no automagic) in the special SEM-flash.  I say this because PG036 says we must write a small table to the SEM-flash that tells SEM where the files are located in the SEM-flash.

I read from pg81 of PG036 (and AR67645) that SEM does not play nicely with multiboot: “SEM controller does not operate when a golden or fallback bistream is loaded by configuration error and fallback..

You may also find good reading at AR54642 about SEM.

Cheers,
Mark

Moderator
Moderator
375 Views
Registered: ‎06-05-2013

Re: SEM and MultiBoot Implementation

Jump to solution
It seems you are targeting 7 series. You can refer to following XAPP https://www.xilinx.com/support/documentation/application_notes/xapp733-multiboot-sem-controller.pdf

From the above XAPP:

A successful MultiBoot event depends on the next bitstream being properly stored at a known address in a non-volatile device suitably interfaced to the FPGA for configuration. The required amount of storage for FPGA configuration depends on the number of bitstreams to be stored, the bitstream size, and a few second-order considerations described in the FPGA configuration user guides.

Designers might also need to consider the organization of SEM controller data. A SEM controller instance uses external data if one or both of these optional features are enabled:

• Error correction by replace
• Error classification

When these optional features are enabled, the SEM controller example design includes a simplified serial peripheral interface (SPI) master through which the SEM controller accesses data in an SPI flash. The SPI flash is dedicated to the SEM controller and independent from any nonvolatile devices used for FPGA configuration

Thanks
Harshit
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
366 Views
Registered: ‎01-22-2015

Re: SEM and MultiBoot Implementation

Jump to solution

@harshit   Thank you!

@400garrison 

     I also have to JTAG-program the SEM flash?
From excellent XAPP733 provided by harshit, I read on page-12:  The constraint file is updated to reflect the changes in top-level I/O pins and assign pin locations suitable for the hardware target. The four I/O pins associated with the optional, user-provided SPI flash for private use of the SEM controller have placeholder location constraints. The user can update these placeholder constraints, if desired.

-and on page-12 of XAPP733: If the optional SPI flash is available as part of the hardware target, the user must obtain and follow the instructions of a third-party programming solution and program the SPI flash separately.

So, I'm now quite sure the answer to your question is yes.

Mark