04-01-2021 10:32 AM
I am working with a design that is using a M25P64 SPI and a Xilinx Spartan 6 FPGA. The prom is programmable and works with a CCLK of 22MHz but does not work with 26MHz. The engineer to design this did not design the board with the capability of dual or quad mode but did terminate the pins as the M25P64 datasheet recommended.
The error that occurs with 26MHz CCLK appears to occur while impact is programming the device at around 400 seconds into programming. The MCS file is quite large with about 199k addresses written to.
We are trying to get a faster boot time so we are trying to have the clk rate set to 26MHz would you know why this is not working? I have evaluated each SPI signal and they seem to have good SI. I have also tried changing the JTAG clock frequency and had no luck.
04-01-2021 12:02 PM
Whats the exact part number of the prom ?
where did you get the M25P64 from ?
I though these had been out of production for a decade or so, and the market was full of grey parts.
Love to know if you have a legitimate source.
04-01-2021 01:24 PM
M25P64-VME6TG is the part number, NUMONYX is the manufacture.
The last time we ordered these parts was years ago. We are aware of the concern of gray parts but do have gates implemented to attempt to prevent this.
04-02-2021 03:04 AM
Sorry, Sounds like you have checked the obvious then,
just check the Spartan 7 data sheet for max SPI configuration speed ,
then its down to change the PROM for one you knows works,