I have a project implemented in a 7 series part. Within the design, we load partial reconfiguration images via the internal ICAPE2 port, after initial configuration. Partial images are loaded from a parallel flash part attached to user IO. Additionally, the system accesses the configuration QSPI, after configuration, to fetch non-configuration data. Access to the QSPI is performed using a custom designed QSPI interface, which attaches to DQ(3:0) data pins and CS pin, and passes the clock pin to the QSPI through the CCLK input on the STARTUPE2 primitive, which we instantiated within the design. The PR loading logic itself feature works fine and has been tested independently. The QSPI works fine and has been tested independently. However, when each of the functions are integrated within the same design and used simultaneously (reconfiguration to ICAP AND QSPI access using SPARTUPE2), the QSPI data gets corrupted.
My current theory is that the use of the ICAPE2 interferes with the STARTUPE2 because the internal configuration circuitry returns to some kind of a programming mode, so the CCLK, DQ, or CS do not reflect what the user logic is doing.
So, my question is: What (if any) is the interaction between the ICAPE2 and the SPARTUPE2? Is there a fundamental issue using these two features in the same design? If not, can they features be used simultaneously? Can using the ICAPE2 somehow impact the CCLK or the dual use DQ and CS pins (these pins are also used during the initial config)? Do I have to use some kind of arbiter to only allow one of these interfaces to be used at a time?
I intend to try and probe the traces between the FPGA and QSPI, however both parts are BGAs so this may be difficult or impossible.