09-11-2019 12:46 PM
In my project, I am using Kintex-7 Board. Kintex-7 has differential clock as input but I require single-ended clock to my design. So, using clock wizard window I am facing problem in setting.Plz help.
09-11-2019 12:58 PM
What is the issue that you are seeing in the Clocking Wizard?
Normally, all you have to do is tell the Clocking Wizard that the source of the input clock will be Single Ended, as in the image below:
Second, when assigning the FPGA pins, you would use only the Positive pin of the Differential Global Clock pair for the input of such single ended clock, and leave the Negative pin floating or grounded.
09-11-2019 01:03 PM - edited 09-11-2019 01:15 PM
As the kintex board has differential clock as the input but to make it compatible with my design which has single ended input... I need to convert differential to single-ended. For that I am using Clock wizard. I have also used IBUFDS but that was giving an error of mismatch between design and probe files.
09-11-2019 01:29 PM
Instead of using and IBUFDS, just use an IBUF.
// IBUF: Single-ended Input Buffer // 7 Series // Xilinx HDL Language Template, version 2018.3 IBUF #( .IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards .IOSTANDARD("DEFAULT") // Specify the input I/O standard ) IBUF_inst ( .O(O), // Buffer output .I(I) // Buffer input (connect directly to top-level port) ); // End of IBUF_inst instantiation
You also do not need to declare your module with the input clk_n, since you do not have it. Just declare the clk_p.
09-11-2019 04:31 PM
09-11-2019 07:48 PM
The main concern is kintex-7 evaluation board has system clock as differential clock. So, if I use IBUF in my design, then how can I map it to the system clock of board.
I have attached the screenshot of the user guide of kintex-7 board
09-12-2019 08:48 AM
We are getting confused information here. I understood that you were input our own single-ended clock into the FPGA, not using the existing System Clock, which is differential.
I re-read your initial message and I think we need to make one important clarification: there is no such thing as differential clock inside the FPGA. You seem to be concerned about converting a differential clock into single-ended so you can use it in your design. You do not need to worry about that. Differential clocks are only differential until they pass through the IBUFDS. After that, it becomes single-ended automatically. You do not need to use the MMCM/PLL for that either (unless you need to change the frequency).
The error you are seeing (about clock not found) is most likely because the XDC constraints you have for that clock (assigning it to the correct pins) might be incorrect.
Could you please post the constraints and pin placements you have for that clock, so we can make sure that it's correct?
09-13-2019 01:53 AM
Below are the constraint file (.xdc), I/O planning file, main module file and the error file.
09-13-2019 09:18 AM
Since DIFF_TERM is false, have you verified that your board has a terminating resistor across the clk_p and clk_n inputs?
09-13-2019 09:45 AM