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giovanna.ferrara
Observer
Observer
841 Views
Registered: ‎01-14-2019

Soft Mitigation Error (SEM) IP on Kintex Ultrascale+ FPGA: problem when using DDR4 IP

Hi all,

we have instantiated a SEM IP core in a XCKU9P device without problems (the heartbeat is correctly working).

Then we added to the design a DDR4 Controller IP: to make the Slave Serial Configuration Mode working we had to add a setting:

startup.match_cycle=6

In fact without this specific setting the FPGA programming does not complete (we do not have DONE) using  Slave Serial Configuration Mode, while the JTAG programming correctly completed.

Unfortunately this specific setting (i.e. startup.match_cycle=6) has the side effect that the SEM is not working any more: we do not have heartbeat and the core is blocked in initialization.

Could someone help us: we need to have both DDR4 controller and SEM working.

Thanks

Giovanna

 

5 Replies
iguo
Xilinx Employee
Xilinx Employee
834 Views
Registered: ‎08-10-2008

MIG calibration will grab ICAP which is used by SEM IP so IP fails to initialize.

Add a BUFGCE  before ICAP's clk. After MIG calibration finishes, provide the clock to SEM and make it work after then. 

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giovanna.ferrara
Observer
Observer
822 Views
Registered: ‎01-14-2019

Thanks Iguo!

we could try to implement your suggestion. In the meantime we would like to add that we made a trial keeping the cap_gnt signal to '0' till the  reset of the FPGA was released.

Could we try to keep the cap_gnt='0' longer, 'till the end of the calibration? It should be easier for us.

Thanks

Giovanna

 

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iguo
Xilinx Employee
Xilinx Employee
793 Views
Registered: ‎08-10-2008

That should work as well. 

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653 Views
Registered: ‎02-27-2019

Hello, my name is Gabriele and I am a @giovanna.ferrara's collegue. I will update you.

We have tried two solutions without success:
1) cap_gnt controlled by DDR4 INIT_DONE
2) BUFGCE for icap_clk controlled by DDR4 INIT_DONE

We also connect sem_ultra_0_uart to monitor the situation.
In both situation we see SEM core stopped at initialization (initialization signal HIGH) without activity on heartbeat. Please see below uart log.

SEM_ULTRA_V3_1
SC 01
FS 04
AF 01
ICAP 

We already check SEM behavior in working situation (i.e. removing DDR4 core and "set_property BITSTREAM.STARTUP.MATCH_CYCLE 6").
In this situation we see SEM core in observation (initialization signal goes LOW and observation signal goes HIGH) and heartbeat toggle as expected. Please see below uart log.

SEM_ULTRA_V3_1
SC 01
FS 04
AF 01
ICAP OK
RDBK OK
INIT OK
SC 02
O>

Any suggestion?

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giovanna.ferrara
Observer
Observer
608 Views
Registered: ‎01-14-2019

Dear Iguo, have you seen Gabriele's post? we have tried your suggestions but we did not succeed.

Could you try to support us again?

thanks

Giovanna

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