12-23-2019 02:29 AM
we have instantiated a SEM IP core in a XCKU9P device without problems (the heartbeat is correctly working).
Then we added to the design a DDR4 Controller IP: to make the Slave Serial Configuration Mode working we had to add a setting:
In fact without this specific setting the FPGA programming does not complete (we do not have DONE) using Slave Serial Configuration Mode, while the JTAG programming correctly completed.
Unfortunately this specific setting (i.e. startup.match_cycle=6) has the side effect that the SEM is not working any more: we do not have heartbeat and the core is blocked in initialization.
Could someone help us: we need to have both DDR4 controller and SEM working.
12-23-2019 02:41 AM
MIG calibration will grab ICAP which is used by SEM IP so IP fails to initialize.
Add a BUFGCE before ICAP's clk. After MIG calibration finishes, provide the clock to SEM and make it work after then.
12-23-2019 03:01 AM
we could try to implement your suggestion. In the meantime we would like to add that we made a trial keeping the cap_gnt signal to '0' till the reset of the FPGA was released.
Could we try to keep the cap_gnt='0' longer, 'till the end of the calibration? It should be easier for us.
12-23-2019 04:42 AM
That should work as well.
01-15-2020 07:16 AM
Hello, my name is Gabriele and I am a @giovanna.ferrara's collegue. I will update you.
We have tried two solutions without success:
1) cap_gnt controlled by DDR4 INIT_DONE
2) BUFGCE for icap_clk controlled by DDR4 INIT_DONE
We also connect sem_ultra_0_uart to monitor the situation.
In both situation we see SEM core stopped at initialization (initialization signal HIGH) without activity on heartbeat. Please see below uart log.
SEM_ULTRA_V3_1 SC 01 FS 04 AF 01 ICAP
We already check SEM behavior in working situation (i.e. removing DDR4 core and "set_property BITSTREAM.STARTUP.MATCH_CYCLE 6").
In this situation we see SEM core in observation (initialization signal goes LOW and observation signal goes HIGH) and heartbeat toggle as expected. Please see below uart log.
SEM_ULTRA_V3_1 SC 01 FS 04 AF 01 ICAP OK RDBK OK INIT OK SC 02 O>
01-21-2020 01:34 AM