01-25-2018 06:40 PM - edited 01-25-2018 06:41 PM
I am a new. And I am trying to configure Spartan-3e via jtag pins. I write a procedure refer to the svf file generated by
IMPACT for xc3s1200e and xcf04s(My board is NEXYS2) . When i tried to dowanload bit files through this procedure , something wrong happened. If i download a bit file with simple logic, it works well. But when i download a bit file with complex logic, it can not work and the DONE pin not goes high after configuration. I guess maybe a mistake happened in CRC check when complex bit file is downloaded. But i haven't found the reason yet, and don't know how to fix it.
The SVF file generated by IMPACT has been attached in the following.
Any help will be appreciated, thank you!
01-28-2018 09:26 PM
could you also share the status registers of the fpga in both the cases which can be read through impact tool.
Also have you tried normal bit file configuration of the fpga instead of using the svf file for the failing case?
02-02-2018 07:09 PM
No, i control the jtag pins directly instead of ISE's Impact. Now I have downloaded some bit files correctly
via jtag pins. But i found another problem. When i tried to read a bit file with complex logic, an unexpected
eof happened before it reached to the real end of this bit file, which led to the failure of spartan-3e configuration.
However, the ISE's Impact can download this bit file correctly.
I can not find the reason, can you help me, thank you!
02-05-2018 02:22 AM
what is the JTAG clock frequency you have specified in your control for the complex logic svf file download?
can you try to set the TCK frequency to 1Mhz and see if this helps
04-02-2018 12:09 AM
Can you tell me the function of JTAG Configuration Register. Whether the length of this register(32bits) can
be explained as that i should do update-DR after 32bits data are written into FPGA when i try to configure FPGA
in JTAG mode.