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Visitor
Visitor
1,289 Views
Registered: ‎01-22-2018

Spartan-3e jtag configuration via jtag pins failed

Hi 

     I am a new. And I am trying to configure Spartan-3e via jtag pins. I write a procedure refer to the svf file generated by 

IMPACT for  xc3s1200e and xcf04s(My board is NEXYS2) . When i tried to dowanload bit files through this procedure , something wrong happened. If i download a bit file with simple  logic, it works well. But when i download a bit file with complex logic, it can not work and the DONE pin not goes high after configuration. I guess maybe a mistake happened in CRC check when complex bit file is downloaded. But i haven't found the reason yet, and don't know how to fix it.

        The SVF file generated by IMPACT has been attached in the following.

        Any help will be appreciated, thank you!

hmj1235

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Scholar
Scholar
1,254 Views
Registered: ‎02-27-2008

Are you using ISE's Impact to control the JTAG?

 

Are you using the same version for both?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Moderator
Moderator
1,238 Views
Registered: ‎01-15-2008

could you also share the status registers of the fpga in both the cases which can be read through impact tool.

Also have you tried normal bit file configuration of the fpga instead of using the svf file for the failing case?

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Visitor
Visitor
1,212 Views
Registered: ‎01-22-2018

No, i control the jtag pins directly instead of ISE's Impact. Now I have downloaded some bit files correctly 

via jtag pins. But i found another problem. When i tried to read a bit file with complex logic, an unexpected 

eof happened before it reached to the real end of this bit file, which led to the failure of spartan-3e configuration.

However, the ISE's Impact can download this bit file correctly.

I can not find the reason, can you help me, thank you!

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Moderator
Moderator
1,183 Views
Registered: ‎01-15-2008

what is the JTAG clock frequency you have specified in your control for the complex logic svf file download?

can you try to set the TCK frequency to 1Mhz and see if this helps

https://www.xilinx.com/support/documentation/application_notes/xapp503.pdf

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Visitor
Visitor
1,097 Views
Registered: ‎01-22-2018

Hi

    Can you tell me the function of JTAG Configuration Register. Whether the length of this register(32bits) can

be explained as that i should do update-DR after 32bits data are written into FPGA when i try to configure FPGA

in JTAG mode.

Thank you!

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Moderator
Moderator
1,085 Views
Registered: ‎01-15-2008

jtag configuration register is explained in UG332 page 208

https://www.xilinx.com/support/documentation/user_guides/ug332.pdf 

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