Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎11-24-2009

Spartan 6 Configuration in Master Serial and Master SelecMAP with Platform Flash


We have a board with a Spartan 6 which loads its bitstream from an XCF32P platform flash.  The FPGA is configured with mode pins M[1:0] = "00" to configure in Master SelectMAP.  We notice that in impact we can select or deselct the "parallel" option in the Platform Flash, and the FPGA will successfully configure in both modes with the same MCS file loaded in the PROM, even though the FPGA is bootstrapped to load the bitstream in Master SelectMAP (parallel) mode through the mode pins.  I also record the ~1 second difference in configuration time between serial and parallel modes depending on whether the parallel mode is selected, so we know that it is being configured in both methods

Firstly, is it intended behaviour that a Spartan 6 FPGA set to Master SelectMAP can be successfully configured in Master Serial Mode by a Xilinx Platform Flash?  If so, please could you point me to some documentation or an application/technical note which gives some additional detail on this?

Secondly, we are considering moving to Master Serial mode of configuration to avoid all of the address toggling that occurs during Master SelectMAP loading.  I note that the FPGA mode pins have internal pullups.  Is it acceptable to remove the pulldown resistor on M0 and use the internal pullup to select Master Serial Mode?  The datasheet suggests connecting pins directly to VCCO and Ground to set the mode pins, but I've found that removing the pulldown resistor works.

Thirdly, we already have some devices in the field that have the FPGA configured to Master SelectMAP.  If we start using Master Serial Mode (M[1:0] = "01") for new devices, can we update both the Master Serial and SelectMAP devices with the same MCS image for serial configuration with the FPGA as Master?

Many thanks in advance for your time and assistance in this matter.

0 Kudos
0 Replies