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597 Views
Registered: ‎08-06-2012

Spartan-6 Configuration memory need to configure by PCIe endpoint Interface

Hello Xilinx Forum,

 

        Greetings,

 

       Here I need to configure the Spartan-6 FPGA by any memory(Prom/FLASH/)  by conventional available methods. Once I did the configuration after that, the second Image(Bit or Bin file ) will come from software via PCIe interface(End point implemented in FPGA) . How to interface this data to the configuration memory, since it is connected with configuration bank of the FPGA. If any one already did these kind of configuration kindly help me on this?

 

       From my studies I understand that ICAP_SPARTAN6 primitive will give access to the Configuration registers from Fabric side .. If Yes How to implement this in the design? If Xilinx help on this by any example design it is really helpful

 

Thanks With Regards,

Venkatesh Babu.N

 

      

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2 Replies
527 Views
Registered: ‎08-06-2012

Re: Spartan-6 Configuration memory need to configure by PCIe endpoint Interface

Hello Forum,

 

     Any update on this please. 

 

And let me know the configuration pins can act as normal IO once the FPGA is configured. If Yes then tell me how to do this in implemetation?. what all are the options available?

 

Thanks With Regards,

Venkatesh Babu.N

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516 Views
Registered: ‎01-15-2008

Re: Spartan-6 Configuration memory need to configure by PCIe endpoint Interface

you need to use startup primitive in spartan-6

refer to the following link for virtex-5 and you can design for spartan-6 accordingly

https://www.xilinx.com/support/documentation/application_notes/xapp1020.pdf

 

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