UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Newbie fenris
Newbie
588 Views
Registered: ‎10-18-2018

Spartan 6 Master SPI - same pins for configuration and data exchange

Hi, I am planning to design a board with MCU and Spartan 6. I wonder if it is possible to connect these two devices via 4 SPI lines and use the same pins for configuration and after loading the configuration for data transmission. Based on "Spartan-6 FPGA Configuration" I understand that the appropriate mode is Master SPI. And I understand that I should use MOSI, DIN, CCLK and CSO_B pins, which, after the configuration is finished, are generally available as User I/O pins. Then in the project I can have simply assigned SPI interface written in HDL code to those pins, which I can start using from the moment when DONE pin = 1. Do I understand this thing well? What else should I pay attention to? Have I not overlooked anything important? Can I ask you for advice to make this configuration as useful as possible and to design the PCB correctly? Regards, - fenris
Tags (1)
0 Kudos
5 Replies
Scholar drjohnsmith
Scholar
583 Views
Registered: ‎07-09-2009

Re: Spartan 6 Master SPI - same pins for configuration and data exchange

 

Can I clarify please,

 

Do you mean the fpga as slave or master ?

 

if its mater, it will try to read the flash at start up,

  if slave the fpga will wait to be written to,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Newbie fenris
Newbie
573 Views
Registered: ‎10-18-2018

Re: Spartan 6 Master SPI - same pins for configuration and data exchange

I mean FPGA in Master SPI mode, so I understand it will start configuration after power-on or when PROGRAM_B is driven low. So it seems that my connection needs 6 lines: MOSI, DIN, CCLK , CSO_B, DONE and PROGRAM_B. I'm not sure about INIT_B.

 

I understand there is no Slave SPI mode.

0 Kudos
Scholar drjohnsmith
Scholar
568 Views
Registered: ‎07-09-2009

Re: Spartan 6 Master SPI - same pins for configuration and data exchange

You have this ?

 

https://www.xilinx.com/support/documentation/user_guides/ug380.pdf

 

page 18 shows the slave modes, the slave serial is often used to program the fpga from a MCU,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Newbie fenris
Newbie
553 Views
Registered: ‎10-18-2018

Re: Spartan 6 Master SPI - same pins for configuration and data exchange

Ahh, you're right, Slave serial seems to be a more convenient mode. So in this case, e.g. considering Spartan 6 in TQG144 I have to connect:

- a MCU clock line to the IO_L1P_CCLK_2 pin
- a MCU data line to the IO_L3P_D0_DIN_MISO_MISO1_2 pin

and when the configuration is finished (DONE_2 is HIGH) I can use these two pins freely, so I can configure the SPI interface on them, does it agree?
0 Kudos
Scholar drjohnsmith
Scholar
536 Views
Registered: ‎07-09-2009

Re: Spartan 6 Master SPI - same pins for configuration and data exchange

dont forget the prog_b . init and done pins,

 

do us a diagram 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos