cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
davenmccalla
Visitor
Visitor
1,846 Views
Registered: ‎06-08-2018

Spartan 6 Microprocessor-Driven x8 SelectMAP Configuration not working. DONE never goes high.

Jump to solution

I'm having problems configuring the FPGA using "Microprocessor-Driven SelectMAP Configuration" described in Figure 2-7 of this guide:

 
 
Attached programline.png shows what happens when the PROGRAM pin is toggled. All of the configuration signals look correct. The INIT and BUSY go active while the device is clearing memory.
 
 
Attached initline.png is zoomed out so you can see the INIT line go high and BUSY line go low before I start writing the configuration using x8 bus width. MODE pins are correct when INIT goes high.
 
 
Attached syncword.png is zoomed in on the sync word being written. The first 16 bytes of the file are FF's and the sync word (55 99 AA 66) is bytes 17-20.
 
All of the signals look like Figure 2-8 in the guide except the DONE line never goes HIGH at the end. I can configure the part through the JTAG port, which toggles the DONE pin, so I know it works. The PROGRAM, INIT, and BUSY lines work. I tested the DATA lines using a configuration downloaded through JTAG and they all work. The SUSPEND and HSWAPEN lines are tied to ground. Ten extra CCKLs provided at the end for startup. The microprocessor code works for configuring SpartanXL and Spartan 2 this way.
 
The bit and bin files were created on a command line using the following commands:
%XILINX%\bin\nt64\bitgen.exe U6.ncd -w U6.bit
%XILINX%\bin\nt64\promgen.exe -p bin -w -u 0 U6
The bit file created works when downloaded through JTAG using  iMPACT 14.7.
The bit file is attached but I was unable to attach bin file. The bin file is basically the bit file minus the header at the top and all bytes are bit swapped.
 
What am I missing!?
 
 
programline.png
initline.png
syncword.png
0 Kudos
1 Solution

Accepted Solutions
davenmccalla
Visitor
Visitor
1,879 Views
Registered: ‎06-08-2018

Problem solved.

 

Checking the pinout in ug385 against the schematic symbol in my schematic revealed that D1 and D2 are swapped in the schematic symbol. When looking at the schematic, D1 and D2 appear to be connected to the correct pins, but they are not. Swapping these signals in the layout fixes the problem.

 

Thank you very much.

View solution in original post

0 Kudos
11 Replies
jmcclusk
Mentor
Mentor
1,820 Views
Registered: ‎02-24-2014

In your shoes, there are 2 things I'd try first.    

 

1.   Add another 20 cycles to CCLK at the end, just to make sure the configuration state machine finishes (this probably won't help).

 

2.  reverse the bits in the byte, and try the other orientation.

 

 

Don't forget to close a thread when possible by accepting a post as a solution.
davenmccalla
Visitor
Visitor
1,806 Views
Registered: ‎06-08-2018

Thanks for the reply.

 

I read others who have suggested adding more CCLKs at the end to get DONE to go high, so I've already tried 20, 100, and even 1000 more CCLKs with no luck. I also tried both bit orders.

 

Not sure if there are any clues here, but below is a status of a successful JTAG configuration and an unsuccessful attempt at SelectMAP x8 configuration:

 

JTAG:

[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[2] RESERVED                                                               :         0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[8] RESERVED                                                               :         0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                  :         0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         1
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
'1': Reading status register contents...
[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         0
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         0
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         0
[9] MODE PIN M[0]                                                          :         0
[10] MODE PIN M[1]                                                         :         0
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         0
[13] DONE PIN                                                              :         1
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0

 

SelectMAP x8:

 

'1': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[2] RESERVED                                                               :         0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[8] RESERVED                                                               :         0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                  :         0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
'1': Reading status register contents...
[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         1
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         0
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         0
[9] MODE PIN M[0]                                                          :         0
[10] MODE PIN M[1]                                                         :         1
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         1
[13] DONE PIN                                                              :         0
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0

 

0 Kudos
borisq
Xilinx Employee
Xilinx Employee
1,788 Views
Registered: ‎08-07-2007

hi @davenmccalla

 

1, please note the bit swapping from SelectMAP interface.

 

2, according to status reg, i see GHIGH is low. This indicates sync word is not detected. I suggest you check hardware. for example, SelectMAP configuration requires Vcco bank 2 to be powered. you can double check. JTAG configuration doesn't require VCCO bank2.

 

Thanks,

Boris

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
davenmccalla
Visitor
Visitor
1,776 Views
Registered: ‎06-08-2018

I'm confident I have the correct bit order, although I have tried both.

 

I couldn't find any documentation connecting GHIGH with sync word not detected. The only thing I could find on GHIGH is:

 

GHIGH STATUS (Virtex-6, Spartan-6) / status of GHIGH (Virtex-5, Spartan-3A)
Power-Up State: "0"
Post-Config State:
"1" - The device has properly received its entire configuration data stream. The device is ready to enter the Startup sequence.
"0" - The device does not receive the entire configuration data stream.

 

However, I did check Vcco for bank 2 and it is tied to +3.3V.

0 Kudos
jmcclusk
Mentor
Mentor
1,767 Views
Registered: ‎02-24-2014

Here's an idea..   Create a test design for your fpga with chipscope that captures the data from the uP on the select map interface.   Download this with JTAG, and then check the data that's captured on the select map interface....   is the data good?

Don't forget to close a thread when possible by accepting a post as a solution.
0 Kudos
davenmccalla
Visitor
Visitor
1,762 Views
Registered: ‎06-08-2018

The device responds to the PROGRAM line being toggled by changing the state of INIT and BUSY, and the device does clear it's memory because the INIT and BUSY change back after about 400 uS, but there is no evidence that it's seeing any of the CCLKs or DATA that I'm writing.

 

If I set the Configuration Watchdog Timer (CWDT) to it's minimum value (0x201) using bitgen, will the INIT line go low after 513 CCLKs with all FFs for DATA? The CWDT should timeout if the sync word is not received after 513 CCLKs, but what indicators are there that it did timeout? I tried this and the INIT line stayed high, and reading the status using JTAG show any errors.

 

[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[2] RESERVED                                                               :         0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[8] RESERVED                                                               :         0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                  :         0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
'1': Reading status register contents...
[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         1
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         0
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         0
[9] MODE PIN M[0]                                                          :         0
[10] MODE PIN M[1]                                                         :         1
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         1
[13] DONE PIN                                                              :         0
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0

 

0 Kudos
davenmccalla
Visitor
Visitor
1,742 Views
Registered: ‎06-08-2018

I used a sightly different method to verify the SelectMAP interface pins work. I downloaded a design that uses all of the relevant configuration pins into the part using JTAG:

 

`timescale 1ns / 1ps
module U6(NIOR, ADDR, A, D, CSI, RDWR, CCLK, M);
    input NIOR, ADDR, CSI, RDWR, CCLK;
    input [9:0] A;
    inout [15:0] D;
    input [1:0] M;

    reg [15:0] data;

    assign D = (~NIOR && (A[9:6] == 4'b1000) && (ADDR~^A[5]) && (A[4:0] == 5'b00000)) ? data:16'bz;

    always @(posedge CCLK) begin
        if (!CSI && !RDWR && !M[0] && M[1])
            data <= D;
    end
endmodule

 

Then I commented the lines in the microprocessor code that toggle the program pin and added lines to verify every byte of the configuration that is written. All bytes written were verified to be correct. Here is the microprocessor code:

 

unsigned long byte_cnt;
unsigned char Byte;
FILE * in = fopen("U6.bin", "rb");
if (NULL != in) {
    fseek(in, 0, SEEK_END);
    unsigned long fpga_size = ftell(in);
    fseek(in, 0, SEEK_SET);
    unsigned char* fpga = new unsigned char [fpga_size+1];
    fread(fpga, 1, fpga_size, in);
    fclose(in);
    /* toggle the program signal */
//TEST
//    outportb(BaseAddr+CPLD_REG,0xFF);
//    outportb(BaseAddr+CPLD_REG,0);
//    outportb(BaseAddr+CPLD_REG,0xFF);
//END TEST
    /* allow FPGA enough time to clear its memory */
    /* Delay more than 500 uS */
    usleep(800);
    /* download configuration bytes*/
    unsigned char* BytePtr = fpga;
    for (byte_cnt=0; byte_cnt<fpga_size; byte_cnt++) {
        /* write configuration byte */
        outportb(BaseAddr, *BytePtr);
//TEST
        Byte = inportb(BaseAddr);
        if (Byte != *BytePtr)
            printf("error:%d\n", byte_cnt);
//END TEST
        BytePtr++;
    }
    /* need 10 more clock cycles, one for each startup sequence */
    for (byte_cnt=0; byte_cnt<10; byte_cnt++) {
        /* write dummy byte */
        outportb(BaseAddr,0X00);
    }
    if (NULL != fpga) delete [] fpga;
}
if (0 == (inportb(BaseAddr+CPLD_REG) & MASK1DONE))
    printf("DONE is not high\n");

jmcclusk
Mentor
Mentor
1,729 Views
Registered: ‎02-24-2014

Your verilog code is pretty confusing, since the inputs don't seem to resemble a bytewide select map port.  I assume your hardware interface resembles Figure 2-7 in UG380?      I'm just wondering if you've been the victim of a pin swap by the PCB layout tool, and possibly the data byte is scrambled in some odd fashion.

 

 

Don't forget to close a thread when possible by accepting a post as a solution.
0 Kudos
davenmccalla
Visitor
Visitor
1,724 Views
Registered: ‎06-08-2018

The line that reads back the latched data may be confusing. It's basically doing some address decoding looking for the base address of the card (0x200 or 0x220) depending on whether the ADDR jumper is populated or not.

 

assign D = (~NIOR && (A[9:6] == 4'b1000) && (ADDR~^A[5]) && (A[4:0] == 5'b00000)) ? data:16'bz;

 

The following section only latches data on the rising edge of CCLK if:

1. CSI is active. This pin is driven from a CPLD and is always low.

2. RDWR configured for writing configuration, not read back. This pin is tied to ground.

3. MODE pins are set to Slave SelectMAP mode, M0 = low and M1 is high.

 

   always @(posedge CCLK) begin
        if (!CSI && !RDWR && !M[0] && M[1])
            data <= D;
    end

 

The fact that I can read back every byte that I write tells me that CSI, RDWR, M0, M1 are configured correctly and that CCLK and D[7:0] functioning.

 

The data lines in the schematic have been checked several times. I'll check the layout to make sure pins didn't get swapped in a footprint.

 

0 Kudos
jmcclusk
Mentor
Mentor
1,347 Views
Registered: ‎02-24-2014

I understand your readback method now...  It's not bad, except that it won't detect swapped pins on the data bus.   This is why I thought Chipscope would let you determine the validity of the data just by a visual inspection of the captured bytes.

Don't forget to close a thread when possible by accepting a post as a solution.
0 Kudos
davenmccalla
Visitor
Visitor
1,880 Views
Registered: ‎06-08-2018

Problem solved.

 

Checking the pinout in ug385 against the schematic symbol in my schematic revealed that D1 and D2 are swapped in the schematic symbol. When looking at the schematic, D1 and D2 appear to be connected to the correct pins, but they are not. Swapping these signals in the layout fixes the problem.

 

Thank you very much.

View solution in original post

0 Kudos