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logison
Observer
Observer
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Registered: ‎03-05-2013

Spartan-6 SPI power supply voltages

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Hello,

 I want to design a board with configuration flash as shown on fig.2-12 in UG380. FPGA: XC6SLX45-3FGG484, flash: M25P16.

The problem is that in my application all the fpga banks must be powered 2.5V while minimum power supply voltage for M25P16 is 2.7V. Will it work if I will use (UG380/Fig.2-12) VCCO_2/VCCAUX=2.5V and VCC(M25P16)=3V ? Btw, what is the recommended value of a resistor between DIN and Q?

 

Regards,

Mariusz

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austin
Scholar
Scholar
11,346 Views
Registered: ‎02-27-2008

The Vcco_2 for the pullups is not the Vcc of the SPI flash, so yes (with that change),

 

As the enable and other pins on the SPI flash get tied to the correct supply (not Vcco_2).

 

With the pullups to 2.5v, everything should work just fine.

 

The series R is for signal integrity, and can be 51 to 120 ohms, if needed.

 

So, relabeling Fig 12-2 as above, yes.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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austin
Scholar
Scholar
6,010 Views
Registered: ‎02-27-2008

l,

 

The Vccint, Vccaux, and Vcco values must be inside the recommended values shown in Table 2 of the data sheet.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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logison
Observer
Observer
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Registered: ‎03-05-2013

Yes, I know it. In my case Vccint=1.2V, Vccaux=2.5V, Vcco_2=2.5V but supply voltage of the M25P16 (Vcc) is NOT 2.5V because it is below the operating range of a flash. For this reason I use Vcc=3V. Take a look at Fig.2-12 of the UG380 and replace ONLY the flash power supply (Vcco_2=2.5V) with Vcc=3V. Will it work?

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austin
Scholar
Scholar
11,347 Views
Registered: ‎02-27-2008

The Vcco_2 for the pullups is not the Vcc of the SPI flash, so yes (with that change),

 

As the enable and other pins on the SPI flash get tied to the correct supply (not Vcco_2).

 

With the pullups to 2.5v, everything should work just fine.

 

The series R is for signal integrity, and can be 51 to 120 ohms, if needed.

 

So, relabeling Fig 12-2 as above, yes.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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logison
Observer
Observer
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Registered: ‎03-05-2013

That's what I wanted to know. Thanks a lot.

 

Regards,

Mariusz

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