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Visitor
Visitor
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Registered: ‎07-23-2020

Spartan 6 UCF to Spartan 7 XDC

In the Spartan 6 UCF file, I have:

CONFIG VCCAUX=3.3; 

When I converted the UCF to XDC, though, the above CONFIG keyword throws back an error. How do I represent the above instantiation of VCCAUX in the XDC format?

Also, I wanted to get some clarification on the UCF to XDC migration on the pin assignments.

Spartan 6: NET "EN_p15KV" LOC = "D6" | IOSTANDARD = LVCMOS33 | DRIVE = 24;

My understanding of the Spartan 7 XDC equivalent is the following: 

set_property PACKAGE_PIN D6 [get_ports EN_p15KV]
set_property IOSTANDARD LVCMOS33 [get_ports EN_p15KV]
set_property DRIVE 24 [get_ports EN_p15KV]

Is this correct? or is there another way to represent the DRIVE = 24? I have found documentation regarding the IOSTANDARD, but I have not found anything concerning DRIVE, or CLOCK_DEDICATED_ROUTE

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

Spartan-6 offers a selectable VCCAUX @ 2.5V or 3.3V:

forums_s6_2_s7_p1.png

Spartan-7 only offers a single VCCUAX @ 1.8V:

forums_s6_2_s7_p2.png

Therefore, there is no XDC constraint required for VCCAUX.

In terms of IO constraints, your example was fine:

set_property PACKAGE_PIN D6 [get_ports EN_p15KV]
set_property IOSTANDARD LVCMOS33 [get_ports EN_p15KV]
set_property DRIVE 24 [get_ports EN_p15KV]

 You could also take advantage of the -dict switch to define in a single line:

set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS33 DRIVE 24 } [get_ports EN_p15KV]

Please note that LVCMOS33 only supports DRIVE strengths of 4, 8, 12, or 16 mA in HR IO Banks.

forums_s6_2_s7_p3.png

You will want to choose LVTTL if you desire a drive strength of 24 mA.

I hope this helps.

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Visitor
Visitor
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Registered: ‎07-23-2020

This is very helpful, thank you. As far as changing to LVTTL, is it ok to have some defined as LVCMOS33 and some as LVTTL, or do all of the pins have to be the same? Are there any risks to converting from LVCMOS33 to LVTTL or it is as simple as changing the name?
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Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

Q1:  Is it ok to have some I/O defined as LVCMOS33 and some as LVTTL, or do all of the pins have to be the same?
A1:  In the case of LVCMOS33 and LVTTL, you can have a mixture.  You will want to reference the 7 Series FPGAs SelectIO Resources User Guide (UG471; v1.10; pp 97-100) under the Rules for Combining I/O Standards in the Same Bank section.

Q2:  Are there any risks to converting from LVCMOS33 to LVTTL or it is as simple as changing the name?
A2:  It really depends on what device you are interfacing to as to guarantee the VIL, VIH, VOL, and VOH levels are compatible.  Please reference the Spartan-7 FPGAs Data Sheet:  DC and AC Switching Characteristics (DS189; v1.9; p 9) under Table 8: SelectIO DC Input and Output Levels for VIL, VIH, VOL, and VOH levels for LVTTL and LVCMOS33.

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Visitor
Visitor
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Registered: ‎07-23-2020

Another thing I noticed: because VCCAUX is now only referential to 1.89 V, will that cause issues since I am using LVCMOS33 which has a reference voltage of 3.3? Or are those two completely separate pieces?
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