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Observer
Observer
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Registered: ‎03-20-2018

Spartan-6 custom configuration scheme fails when bitstream has extra data

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Hi buddies,
I'm currently creating a custom configuration solution for Spartan-6 FPGA (XC6SLX150).
Following UG380 (v2.8) and especially XAPP502 (v1.6.1), I managed to store FPGA bitstream in a Non-Volatile Memory, and use a separate controller to read from the Non-Volatile Memory and feed the data into Spartan-6 thru 8-bit Master SelectMAP configuration interface.
When the exact bitstream is fed into the FPGA without any extra data at the beginning, everything is good.
However, when extra padding data (all FFs) are added before the bitstream, configuration fails. I tried 4Mbits and 80Mbits of leading pad data, and they both failed.
Question is:
I had thought that Spartan-6 will run through all leading pad data and look for SYNC Word, but now it seems Spartan-6 just does NOT accept any extra pad data (all FFs or whatever) before the bitstream. Is this right?
Best Regards & thanks ~~

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Moderator
Moderator
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Registered: ‎01-15-2008

in my previous post i mentioned 256 bytes, it must be 512 clock cycles and it applies to serial/spi configuration.

i.e. you must avoid the user data/padding for serial configuration beyond 512 clock cycles of accessing the config data.

https://www.xilinx.com/support/answers/41813.html

 

can you post the status registers of the fpga when the fpga doesnt come up in master selectmap mode?

 

when the configuration data is sent after some pads are you making sure that sync word sent is aligned with master select data pins?

spartan-6 has the autodetect for the bus width of selectmap whereas virtex-5 has seperate bus width detection pattern

 

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Moderator
Moderator
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Registered: ‎01-15-2008

how many bytes of pad data(FF's) you are providing?

if you are using more than 256 bytes, then can you reduce it to less than 256 bytes and see if that helps

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Observer
Observer
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Registered: ‎03-20-2018

Thanks for your reply; I tried two scenarios: 4Mbits and 80Mbits pad data, and they both failed.

 

I actually went thru the UG380 (v2.8) text thoroughly and on page 77, it says:

No packet processed by the FPGA until the Sync word is found.

In my understanding or guessing, this sentence implies that,

(1) an unlimited amount of leading pad data is acceptable, and

(2) if Spartan-6 do not find SYNC Word pattern in incoming data, then it will keep looking for it.

But, test results do not agree with my guessings -,-

 

BTW:

However, my previous guessings might not work for Spartan-6, but it DOES work for Virtex-5.

In a similar custom configuration solution targed for Virtex-5 XC5VFX200T, I can put 80Mbit or 160Mbits of leading pad data before the real bitstream, and they're both OK for Virtex-5.

Seems like Spartan-6 and Virtex-5 are using different internal configuration control logic?

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Moderator
Moderator
1,224 Views
Registered: ‎01-15-2008

in my previous post i mentioned 256 bytes, it must be 512 clock cycles and it applies to serial/spi configuration.

i.e. you must avoid the user data/padding for serial configuration beyond 512 clock cycles of accessing the config data.

https://www.xilinx.com/support/answers/41813.html

 

can you post the status registers of the fpga when the fpga doesnt come up in master selectmap mode?

 

when the configuration data is sent after some pads are you making sure that sync word sent is aligned with master select data pins?

spartan-6 has the autodetect for the bus width of selectmap whereas virtex-5 has seperate bus width detection pattern

 

View solution in original post

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Observer
Observer
917 Views
Registered: ‎03-20-2018

Hi kkn, thanks for your kind reply.

 

(1) I read your post (https://www.xilinx.com/support/answers/41813.html), in which you mentioned in Master SPI/Serial configuration modes extra leading data should not exceed 512 clock cycle, while in Master SelectMAP configuration mode ( we had donfiguration problem in this mode) you did not mention such restriction.

 

(2) The PCB board is not currently available so that I do not have access to the STATus Register for the time being.
However, upon your suggestion I read the STAT reg definition in ug380 carefully, and to my surprise I found Spartan-6 has something called "Configuration WatchDog timer (CWDT)":
"The Spartan-6 FPGA watchdog timer is used tomonitor detection of the sync word. When the watchdog timer times out, the configuration logic increments the strike count and attempts to reconfigure if ..." (ug380 page 136)
and,
"The watchdog timer is only active in master configuration modes." (ug380 page 132)
I think the descriptions about WatchDog Timer has clearly answered my question:
In master modes, the existence of WatchDog means that if too many extra padding data is added before bitstream, then configuration will fail -- This is my personal understanding.

 

(3) We did make sure that sync word sent to Spartan-6 is aligned to 8-bit data boundaries; that is, AA, 99, 55, 66 are each communicated as a 8-bit data on D0-D7.

 

(4) Virtex-5 (ug191) does NOT have WatchDog Timer that monitors the detection of SYNC Word, and this is clearly a major difference between S6 and V5.