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marton
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Registered: ‎02-20-2021

Spartan 6 external clock shift register

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Hey all,

I need to interface a chip which gives a bunch of pins with data and a clock pin. The clock is at 40Mhz.

The FPGA board I'm using for this is a Mojo v3, with a Spartan 6 chip. I am programming it in verilog, I'm still pretty new to this technology and environment.

I thought for reading this data I will need a shift register. I implemented a simple one using a module and it almost works fine.

My issue is that my always block is triggered both for clock AND data going high. So for each high pin I am getting two bits.

I made a test setup to see what's happening, used an avr to generate the clock and data signals. For now I'm using a 8bit shift register, wired directly to the FPGA leds. Checked the signals with a scope and they are pretty clean. Also, the setup is stable, I always get two bits for high and one for low. The pin I am using is a GCLK according to the user guide. I also tested the code with the internal clock, and it works perfectly with it. So my assumption would be that the code is okay but I'm missing some settings when using a pin as clock, but can't figure out what.

This is the relevant part from my .ucf file:

 

NET "clock" LOC = P92 | IOSTANDARD = LVCMOS18;
NET "data" LOC = P94 | IOSTANDARD = LVTTL;

 

 

And this is the verilog module for the shift register.

 

module flipD #(parameter SIZE =  (
    input clock,
    input D,
    output [SIZE - 1 : 0] Q
  );

  reg [SIZE - 1 : 0] q;
  assign Q = q;

  always @(posedge clock) begin
    q = q << 1;
    q[0] = D;
  end

endmodule

 

 

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308 Views
Registered: ‎01-22-2015

@marton 

I am familiar with doing this using Vivado, the Spartan-7, and VHDL.  However, my knowledge of ISE, the Spartan-6, and Verilog is all pretty rusty.  So, I can tell you what to do but I can’t tell you exactly how to do it.

Here is one way to capture the LVDS data with the FPGA:

First, brush up your knowledge of the digital register, because we will use a register inside the FPGA to capture the LVDS data.  Recall that a register captures incoming data on the rising-edge of a clock.  Also recall that the time between clock transitions and data transitions must satisfy setup and hold requirements of the register.  Generally, setup and hold requirements of the register are satisfied if the data is center-aligned (ie. data transitions occur on the falling-edge of the clock). 

So, the objective is to get center-aligned data at the register inside the FPGA that captures the LVDS data.  This can be done using the simple combination of a DCM and register as shown in Fig 2-4 below from document UG382.  The idea being that you use the DCM to place either a positive or negative phase shift on the interface clock so that data is center-aligned when it (and the clock) reaches the register.  Make sure that the interface clock enters the FPGA on a global clock (GCLK) pin.  So, read up on using the DCM.
UG382_SSCA_input.jpg

 

Next, learn how to specify that the register (shown in Fig 2-4) is to be placed in the IOB of the FPGA.  In document, UG381, this is called the “pack I/O register/latches into IOBs” attribute.  The idea here is that you want to lock the capture register into a known position right next to the pins that bring LVDS data into the FPGA.  The DCM will automatically be locked into position since each GCLK pin can reach only one DCM (I think?).  Then, with everything locked down, you will only need to adjust DCM phase once to get center-aligned data at the capture register.

Next, you could fiddle with DCM phase until the capture register is reliably capturing the incoming LVDS data.  This can be time consuming because the procedure is: 1) set DCM phase,  2) generate the bitstream, 3) load bitstream to FPGA and see if things are working, 4) if not, then return to step 1) and try a new phase setting for the DCM. 

Instead of using the fiddling method to get things working, you can place timing constraints for the interface into your .ucf constraints file.  Then, ISE timing analysis will tell you when (after fiddling with DCM phase) the capture register is reliably capturing the incoming LVDS data.  I think the constraint you need is called OFFSET IN and is described in document, UG625.  You will also need a constraint telling ISE about the interface clock.  I think this is called the TIMESPEC constraint which is also described in document UG625.

Cheers,
Mark

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5 Replies
drjohnsmith
Teacher
Teacher
498 Views
Registered: ‎07-09-2009

look at the simulation not the board 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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400 Views
Registered: ‎01-22-2015

@marton 

I need to interface a chip which gives a bunch of pins with data and a clock pin. The clock is at 40Mhz.

It sounds like you are trying to build a "source synchronous input" interface between the FPGA and your external "chip". 

If this is what you are trying to do then it is a tough problem for a beginner.  The main difficulty is that you must ensure a "correct" relationship between clock and data from the external device when they reach the data-capture register in the FPGA.

Please tell us more about the "chip" that is sending data to the FPGA.  For example, can you give us a part-number or a timing diagram between the clock and data outputs of the chip?

Cheers,
Mark

marton
Visitor
Visitor
373 Views
Registered: ‎02-20-2021

I am trying to do an LVDS interface with the FPGA in order to communicate with a CIS (contact image sensor).
The chip is http://rohmfs.rohm.com/en/products/databook/datasheet/ic/interface/lvds/bu90r104-e.pdf.

My main concern is whether the FPGA can or can not be configured to run its logic on an external clock, or in the end it does rely in its internal clock and has to sync it somehow with the external one.

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bruce_karaffa
Scholar
Scholar
350 Views
Registered: ‎06-21-2017

The FPGA does not have an internal clock, except for one that is only used for configuration in certain modes.  Your board will have an oscillator feeding a clock pin on the FPGA that typically you will use as a master clock but if you have a constantly running clock coming into another clock pin, you may use it.  You should look at the clock primitives for your device such as BUFG and DMM to see how to set up the clock tree correctly.

0 Kudos
309 Views
Registered: ‎01-22-2015

@marton 

I am familiar with doing this using Vivado, the Spartan-7, and VHDL.  However, my knowledge of ISE, the Spartan-6, and Verilog is all pretty rusty.  So, I can tell you what to do but I can’t tell you exactly how to do it.

Here is one way to capture the LVDS data with the FPGA:

First, brush up your knowledge of the digital register, because we will use a register inside the FPGA to capture the LVDS data.  Recall that a register captures incoming data on the rising-edge of a clock.  Also recall that the time between clock transitions and data transitions must satisfy setup and hold requirements of the register.  Generally, setup and hold requirements of the register are satisfied if the data is center-aligned (ie. data transitions occur on the falling-edge of the clock). 

So, the objective is to get center-aligned data at the register inside the FPGA that captures the LVDS data.  This can be done using the simple combination of a DCM and register as shown in Fig 2-4 below from document UG382.  The idea being that you use the DCM to place either a positive or negative phase shift on the interface clock so that data is center-aligned when it (and the clock) reaches the register.  Make sure that the interface clock enters the FPGA on a global clock (GCLK) pin.  So, read up on using the DCM.
UG382_SSCA_input.jpg

 

Next, learn how to specify that the register (shown in Fig 2-4) is to be placed in the IOB of the FPGA.  In document, UG381, this is called the “pack I/O register/latches into IOBs” attribute.  The idea here is that you want to lock the capture register into a known position right next to the pins that bring LVDS data into the FPGA.  The DCM will automatically be locked into position since each GCLK pin can reach only one DCM (I think?).  Then, with everything locked down, you will only need to adjust DCM phase once to get center-aligned data at the capture register.

Next, you could fiddle with DCM phase until the capture register is reliably capturing the incoming LVDS data.  This can be time consuming because the procedure is: 1) set DCM phase,  2) generate the bitstream, 3) load bitstream to FPGA and see if things are working, 4) if not, then return to step 1) and try a new phase setting for the DCM. 

Instead of using the fiddling method to get things working, you can place timing constraints for the interface into your .ucf constraints file.  Then, ISE timing analysis will tell you when (after fiddling with DCM phase) the capture register is reliably capturing the incoming LVDS data.  I think the constraint you need is called OFFSET IN and is described in document, UG625.  You will also need a constraint telling ISE about the interface clock.  I think this is called the TIMESPEC constraint which is also described in document UG625.

Cheers,
Mark

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