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logicaledge
Observer
Observer
360 Views
Registered: ‎12-16-2014

Spartan-7 Master SPI flash access prior to configuration

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Is it safe to access the configuration SPI flash on a Spartan-7 (master SPI config mode) by an external device connected directly to the SPI flash pins by holding INIT_B low? In other words, are the S7's SPI flash config I/O kept tristated fully until INIT_B is released after power-up?

The specific scenario in view is production programming of SPI devices installed on the board but not yet programmed, without access to Xilinx toolchain.

I've searched UG470, the forums, various app notes, and have found only circumstantial info regarding this scenario, i.e. nothing definitive.

e.g. UG470 states in the "Configuration Sequence" section: "During this time, with the exception of a few configuration output pins, the I/Os are placed in a High-Z state through the use of the global three-state (GTS) and will have an internal pull-up if PUDC_B is low."

 

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iguo
Xilinx Employee
Xilinx Employee
297 Views
Registered: ‎08-10-2008

This should work. Holding INIT_B can place CCLK and data lines in tri-state.

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iguo
Xilinx Employee
Xilinx Employee
298 Views
Registered: ‎08-10-2008

This should work. Holding INIT_B can place CCLK and data lines in tri-state.

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Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------

View solution in original post

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logicaledge
Observer
Observer
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Registered: ‎12-16-2014

Excellent. Thank you

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stevecurrie
Participant
Participant
256 Views
Registered: ‎01-26-2016

Can you spell out in detail which pins are NOT tristated while INIT_B is held low? The guide only says that most of the pins are tristated, it doesn't say which ones are not.

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logicaledge
Observer
Observer
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Registered: ‎12-16-2014

In case anyone else comes inquiring about this topic, I subsequently discovered that the SP701 provisions for this SPI device programming approach with a separate header connected to the QSPI signals, and a switch to hold INIT_B low.

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