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176 Views
Registered: ‎06-18-2019

Spartan 7 (XC7S25-CSGA324) pin details needed

Hi all,

I was searching for pin definitions of XC7S25-CSGA324 FPGA. Like which pin is clock input and which pin is IO and which pin may be used for other purposes(dual purpose). 

To my surprise, and frustration, I couldn't find that anywhere on net in any document. 

Have I missed something or they are really not available? 

If they are not available then how can we know which pin is what? 

Help needed.

Thanks

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-27-2018

Hi @tahirsengine1 , 

You can find the pin information that you are looking for, of any device, in Vivado itself. You can create io pin planning project and see pin info in io planning view.

Please watch Vivado io planning overview quick take video once for complete details. 

~Chinmay

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Registered: ‎06-18-2019

Hi, 

I saw that, but is there any document for such info as previously was available? 

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Registered: ‎06-21-2017

Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

See https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf

see "pin definitions" page 28 (current v1.18 revision) for the naming/decoding convention.

then page 69 for the the specific device/package pin listing for S7.

which takes you here:

https://www.xilinx.com/support/package-pinout-files/spartan-7-pkgs.html

for the ASCII listing.

Cheers,

bt