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Observer
Observer
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Registered: ‎10-02-2015

Spartan 7 slave serial configuration issue

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Hi,

I'm trying to program a Spartan 7 FPGA (XC7S15) through the Slave Serial Interface managed by the PS of a Zynq device.

I generated a .bin file (no header) with Vivado 2018.3 and tested it with the JTAG programmer. Everything worked fine, therefore the file is good.

Then, I tried to send the same bitstream through the SlaveSerial Interface. INIT_B is always high, whereas DONE is low.

I checked the timing of the signals with an oscilloscope, but I don't see issues. The clock frequency is 500kHz, the setup and hold time requirements are not violated. There are no ringings in the signals.

I tried also to issue more clock cycles after the end of the bitstream file, as suggested in (https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf), but nothing changes.

I checked the sync word (0xAA995566) with an oscilloscope and it seems correct. The bits sent are the following:

1010 1010 1001 1001 0101 0101 0110 0110

where bits are sent from left to rigth, i.e. the leftmost bit is the first to be sent.

I checked the BOOT_STATUS and CONFIG_STATUS registers through the Vivado Hardware Manger and their values are the following:

REGISTER.BOOT_STATUS 00000000000000000000000000000000
REGISTER.BOOT_STATUS.BIT00_0_STATUS_VALID 0
REGISTER.BOOT_STATUS.BIT01_0_FALLBACK 0
REGISTER.BOOT_STATUS.BIT02_0_INTERNAL_PROG 0
REGISTER.BOOT_STATUS.BIT03_0_WATCHDOG_TIMEOUT_ERROR 0
REGISTER.BOOT_STATUS.BIT04_0_ID_ERROR 0
REGISTER.BOOT_STATUS.BIT05_0_CRC_ERROR 0
REGISTER.BOOT_STATUS.BIT06_0_WRAP_ERROR 0
REGISTER.BOOT_STATUS.BIT07_0_SECURITY_ERROR 0
REGISTER.BOOT_STATUS.BIT08_1_STATUS_VALID 0
REGISTER.BOOT_STATUS.BIT09_1_FALLBACK 0
REGISTER.BOOT_STATUS.BIT10_1_INTERNAL_PROG 0
REGISTER.BOOT_STATUS.BIT11_1_WATCHDOG_TIMEOUT_ERROR 0
REGISTER.BOOT_STATUS.BIT12_1_ID_ERROR 0
REGISTER.BOOT_STATUS.BIT13_1_CRC_ERROR 0
REGISTER.BOOT_STATUS.BIT14_1_WRAP_ERROR 0
REGISTER.BOOT_STATUS.BIT15_1_SECURITY_ERROR 0
REGISTER.BOOT_STATUS.BIT16_RESERVED 0000000000000000


REGISTER.CONFIG_STATUS 01110000000000000001111100001100
REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR 0
REGISTER.CONFIG_STATUS.BIT01_DECRYPTOR_ENABLE 0
REGISTER.CONFIG_STATUS.BIT02_PLL_LOCK_STATUS 1
REGISTER.CONFIG_STATUS.BIT03_DCI_MATCH_STATUS 1
REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS 0
REGISTER.CONFIG_STATUS.BIT05_GTS_CFG_B_STATUS 0
REGISTER.CONFIG_STATUS.BIT06_GWE_STATUS 0
REGISTER.CONFIG_STATUS.BIT07_GHIGH_STATUS 0
REGISTER.CONFIG_STATUS.BIT08_MODE_PIN_M[0] 1
REGISTER.CONFIG_STATUS.BIT09_MODE_PIN_M[1] 1
REGISTER.CONFIG_STATUS.BIT10_MODE_PIN_M[2] 1
REGISTER.CONFIG_STATUS.BIT11_INIT_B_INTERNAL_SIGNAL_STATUS 1
REGISTER.CONFIG_STATUS.BIT12_INIT_B_PIN 1
REGISTER.CONFIG_STATUS.BIT13_DONE_INTERNAL_SIGNAL_STATUS 0
REGISTER.CONFIG_STATUS.BIT14_DONE_PIN 0
REGISTER.CONFIG_STATUS.BIT15_IDCODE_ERROR 0
REGISTER.CONFIG_STATUS.BIT16_SECURITY_ERROR 0
REGISTER.CONFIG_STATUS.BIT17_SYSTEM_MONITOR_OVER-TEMP_ALARM_STATUS 0
REGISTER.CONFIG_STATUS.BIT18_CFG_STARTUP_STATE_MACHINE_PHASE 000
REGISTER.CONFIG_STATUS.BIT21_RESERVED 0000
REGISTER.CONFIG_STATUS.BIT25_CFG_BUS_WIDTH_DETECTION 00
REGISTER.CONFIG_STATUS.BIT27_HMAC_ERROR 0
REGISTER.CONFIG_STATUS.BIT28_PUDC_B_PIN 1
REGISTER.CONFIG_STATUS.BIT29_BAD_PACKET_ERROR 1
REGISTER.CONFIG_STATUS.BIT30_CFGBVS_PIN 1
REGISTER.CONFIG_STATUS.BIT31_RESERVED 0

I see there is a BAD_PACKET_ERROR, but I don't know what this means.

I used Matlab to generate other three configurations files: 1) with swapped bytes, 2) with reversed bit order 3) with both swapped bytes and reversed bit order. I used those three files, but none of them worked. Moreover, when using those three files, I didn't get the BAD_PACKET_ERROR. Therefore, I think that the original byte/bit order was correct.

I used a HEX Editor to modify the generated bin file, to see if the FPGA could recognize the errors. I changed the IDCODE of the Device (the original was 0x03620093) and set it to 0x03620090 without changing the CRC. Nothing changes, I didn't get any error when using the SlaveSerial Interface: no IDCODE error, no CRC error. I uploaded the modified .bin with the JTAG and this time I got a CRC error. I repeated the test with a new IDCODE 0x0362AA93. This time I got and IDCODE error after programming with the SlaveSerial Interface.

I searched for related posts in this blog, but I didn't find the solution.

Thanks in advance for any help.

Pietro

 

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Observer
Observer
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Registered: ‎10-02-2015

Re: Spartan 7 slave serial configuration issue

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The problem was related to a pull-up resistor that is present on the CCLK_0 pin of the Spartan 7 FPGA I was trying to configure (https://forums.xilinx.com/t5/Other-FPGA-Architectures/State-of-CCLK-0-pin-when-in-Slave-Serial-Mode/m-p/982843/thread-id/35266/highlight/false#M35300).

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Observer
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Registered: ‎10-02-2015

Re: Spartan 7 slave serial configuration issue

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I found that the problem is related to the SPI transmission. Indeed the PS of the Zynq seems to have SPI set with CPOL = 1 and CPHA = 1, which means that the idle level of the clock is high and data are shifted out on the falling edge of the clock. By looking at data and clock signals with the oscilloscope I found that the bitstream is not transmitted all in once, but in packets. Between one packet and the subsequent, the clock signal goes back to the idle state (high), causing the slave to see an unwanted rising edge. Indeed, I read back the bitstream of the FPGA after a correct configuration (performed with the JTAG) and a wrong configuration (performed with the SlaveSerial) using the readback_hw_device tcl function and compared them with a HEX editor. The only differences are 1-bit shifts in some points, which are in agreement with the unwanted rising edge.

At this point I would like to change the CPOL and CPHA settings of the SPI, but I don't know how to do it.

We are using Linux kernel 3.14 on Yocto Fido with meta-xilinx receipes-kernel.

The SPI is described in the device tree:

 

		ps7_spi_1: ps7-spi@e0007000 {
			spidev0: spidev@0 {
				compatible = "linux,spidev";
				spi-max-frequency = <100000>;
				reg = <0>;
			};
			spidev1: spidev@1 {
				compatible = "linux,spidev";
				spi-max-frequency = <100000>;
				reg = <1>;
			};
			spidev2: spidev@2 {
				compatible = "linux,spidev";
				spi-max-frequency = <100000>;
				reg = <2>;
			};
		};

I looked at the documentation (https://github.com/Xilinx/linux-xlnx/tree/master/Documentation/devicetree/bindings/spi) but I didn't find a way to changed CPOL and CPHA. I tried adding the properties spi-cpol = <0> and spi-cpha = <0>, but it didn't work out.

Moreover, if I look at the clock signal, it has a frequency of 500kHz, which is not in agreement with spi-max-frequency = <100000>.

 

 

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Observer
Observer
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Registered: ‎10-02-2015

Re: Spartan 7 slave serial configuration issue

Jump to solution

The problem was related to a pull-up resistor that is present on the CCLK_0 pin of the Spartan 7 FPGA I was trying to configure (https://forums.xilinx.com/t5/Other-FPGA-Architectures/State-of-CCLK-0-pin-when-in-Slave-Serial-Mode/m-p/982843/thread-id/35266/highlight/false#M35300).

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