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Sabulanis
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Registered: ‎11-03-2020

State of Config Pins during partial power-up of Spartan-7

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Hello,

i would like to use a flash programmer to directly program a QSPI flash memory attached to a XC7S50 during production. The flash is connected to the QSPI interface of the FPGA and used as configuration memory.

For programming , i would need to power up the 3.3V supply, but not the 1V and 1.8V supplies required by the FPGA, and would like to know if this is a safe procedure. In what state are the QSPI config pins of the FPGA when only the 3.3V supply is provided? Or which precautions should be taken to use this procedure?

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ddn
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Registered: ‎06-06-2018

@Sabulanis ,

What state do configuration-only pins enter after the configuration completes or fails?

>> It will be in Tri-state.

The data pins are multi-purpose and should become tri-state once configuration ends, but what about the CCLK and FCS_B pins?

>> CCLK and FCS_B will be in tristate.

Regards,
Deepak D N
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ddn
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Registered: ‎06-06-2018

@Sabulanis ,

If you provide only 3.3V FPGA Bank voltage for Master SPI Configuration Mode, no issues. For more information refer Table2-3 in page 34 of UG470 (v1.13.1).

During Configuration, if all the Configuration banks are provided with corresponding voltages as mentioned in Table 2-3, then SPI Configuration Pins will be in active stage. But during power up, SPI Config pins will be in tristate, if you follow power sequencing given in FPGA datasheet, otherwise state of IO is unpredictable.

And all Non Configuration Banks pins status depends on PUDC Pin state. For more information refer this AR#50802 .

Regards,
Deepak D N
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Sabulanis
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Registered: ‎11-03-2020

Thank you very much, so powering the 3.3V supply without the proper power sequence is not a good idea. 

What state do configuration-only pins enter after the configuration completes or fails? I've added a scetch to visualize what i had planned. Basically i want to access the configuration flash directly using an external programmer and want to know which precautions i need to take. The data pins are multi-purpose and should become tri-state once configuration ends, but what about the CCLK and FCS_B pins?

 Untitled Diagram (3).png

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ddn
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146 Views
Registered: ‎06-06-2018

@Sabulanis ,

What state do configuration-only pins enter after the configuration completes or fails?

>> It will be in Tri-state.

The data pins are multi-purpose and should become tri-state once configuration ends, but what about the CCLK and FCS_B pins?

>> CCLK and FCS_B will be in tristate.

Regards,
Deepak D N
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