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Adventurer
Adventurer
268 Views
Registered: ‎10-29-2017

Tandem PCIe with field updates for Zynq

Hi, 

    I can see Xilinx has provided demo videos for each type of TANDEM PCIe (Tandem PROM, Tandem PCIe, Tandem PCIe with field updates). But they are for US+ devices such as kintex, virtex. Why there are no such example demos for Zynq devices? If it is already available, please provide the link or if it is not available, does design procedure for zynq remains same as shown for kintex and virtex?

Kindly help on this. 

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5 Replies
Xilinx Employee
Xilinx Employee
243 Views
Registered: ‎11-17-2008

Re: Tandem PCIe with field updates for Zynq

The solution for ZU+ is 95% the same as the solution for other US+ devices.  The one difference is that for Tandem PCIe, the user must request access to the MCAP for stage 2 or Field Update (partial bitstream) delivery by setting the pcap_pr register.  The solution in terms of implementing the PL side to separate the PCIe IP and so on is all the same.

thanks,

david.

Adventurer
Adventurer
227 Views
Registered: ‎10-29-2017

Re: Tandem PCIe with field updates for Zynq

Thank you. 

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Adventurer
Adventurer
220 Views
Registered: ‎10-29-2017

Re: Tandem PCIe with field updates for Zynq

Hi, 

   I'm working with zynq device XCZU19EG enabling 'Tandem PCIe with field updates'. I have many user I/O in the design assigned in bank 65,which are not related to PCIe. With reference to PG213, page no. 113, by using OBUFTDS, I tried to declare those pins as output pins in bank 65. But I'm getting placement failed saying the following error.

image.png

Is it possible to use user I/O pins in bank 65 or my declaration is wrong?

Please help on this. 

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Xilinx Employee
Xilinx Employee
156 Views
Registered: ‎11-17-2008

Re: Tandem PCIe with field updates for Zynq

@sumaiya,

I can't see the image you tried to post, but I expect it is an error in regards to the pblock ownership of stage 1 elements.  If it is the error I am thinking of, you must assign all these IO resources to the stage1 IO pblock, and it should give you the syntax later in the error message.  (perhaps you've figured this out already, given how old this post is)

Note that anything placed in this bank 65 pblock must be part of the static design, not the update_region (dynamic) part of the design.  The Partial Reconfiguration flow requires a 1-to-1 mapping of the Reconfigurable Partition pblock and the single top-level of the hierarchy that is defined as dynamic.  If the IO in question are part of the reconfigurable (field update) part of this design, they cannot be placed in bank 65.

thanks,

david.

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Adventurer
Adventurer
110 Views
Registered: ‎10-29-2017

Re: Tandem PCIe with field updates for Zynq

Hi davidd, 

    Thanks for your response. As there was no response on this thread, I posted a new thread for the same and the link is below.

https://forums.xilinx.com/t5/Implementation/Tandem-PCIe-with-field-updates-in-zynq-XCZU19EG/m-p/1022114#M26203

   There it was mentioned to set PERSIST as FALSE in constraint file. 

   What is the apt solution for this? Either not to declare user application I/Os in bank 65 or can set PERSIST as FALSE even though those I/Os are declared in bank 65? What's the difference between these two?

    Can you explain elaborately what cannot be placed in bank 65?

    Please reply asap. 

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