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eswar
Visitor
Visitor
227 Views
Registered: ‎08-24-2021

TclStackFree: incorrect freePtr. Call out of sequence? in 2019,2020 vivado.

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Hello everyone,

I'm Facing a TclStackFree: incorrect freePtr. Call out of sequence? while doing synthesis, I tried 2019,2020 all versions, everywhere it's showing the same.

 

I tried the below suggestions, No Use.

1. Apply the following Tcl command before clicking Run Synthesis in the Vivado IDE, or executing synth_design command via TCL:

set_param synth.elaboration.rodinMoreOptions {set rt::extractNetlistGenomes false}

 

2. Use "Flow Run time optimized" synthesis strategy. Also, try setting "Flatten_hierarchy" to NONE in synthesis settings and see if that helps.

 

3. A similar Issue was resolved by changing the computer name or the path name as seen in the below thread:

https://forums.xilinx.com/t5/Synthesis/TclStackFree-incorrect-freePtr-Call-out-of-sequence/td-p/423929/page/2

 

Can anyone help to resolve this issue..?

Below I attached my Log file, please have a look.

 

 

Thanks

Eswar

 

 

 

 

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seamusbleu
Voyager
Voyager
117 Views
Registered: ‎08-12-2008

Are your next states all, or mostly, just State+1?  If so write your state machine that way and get rid of all/most of the parameters.  Something like attached perhaps.

<== If this was helpful, please feel free to give Kudos, and accept as Solution if it answers your question ==>

View solution in original post

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seamusbleu
Voyager
Voyager
154 Views
Registered: ‎08-12-2008

There is a huge number of parameters in your Part2 module - it would be an interesting test to see of commenting them out (or changing them to constants?) would cause the error to go away.

<== If this was helpful, please feel free to give Kudos, and accept as Solution if it answers your question ==>
eswar
Visitor
Visitor
146 Views
Registered: ‎08-24-2021

Thqu for ur reply , But I didn't understand clearly your point. what do you mean changing them to Constants?

 

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seamusbleu
Voyager
Voyager
139 Views
Registered: ‎08-12-2008

Are you assigning the parameters, or just using their default values?  If the former, I was suggesting commenting out the assignments, if the later, I was suggesting changing them to constants - but that's because I think in VHDL, not verilog.  Basically, can you try to temporarily eliminate the really long list of parameters to see if it affects the error.

<== If this was helpful, please feel free to give Kudos, and accept as Solution if it answers your question ==>
eswar
Visitor
Visitor
135 Views
Registered: ‎08-24-2021

Hi, I can synthesis perfectly from Parameters S4264 - S12770, But when I try to synthesis all parameters (S4264 - S20337) it showing the Tcl stack free (Logfile).

Below I attached a sample code, Maybe have a look.

 

Regards,

Eswar.

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seamusbleu
Voyager
Voyager
118 Views
Registered: ‎08-12-2008

Are your next states all, or mostly, just State+1?  If so write your state machine that way and get rid of all/most of the parameters.  Something like attached perhaps.

<== If this was helpful, please feel free to give Kudos, and accept as Solution if it answers your question ==>

View solution in original post

0 Kudos