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Newbie
Newbie
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Registered: ‎05-30-2011

The IO configuration of xc7a200t-1SBG484C on DIGILENT NEXYS Video Board

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Dear Sirs,

  I suffer a strange problem on this chip and board. Please help,

The common critical is that I set the IO bank to 1.2 V level.

I add a pull-up resistor to 3.3V at the output of the IO FMC_LA02_P outside the FPGA chip.

When we set this IO to several conditions as below, 

1. Set this IO as output and  logic 0 , the voltage of output  is  0  => it's OK.

2. Set this IO as output and  logic 1,  the voltage of output  is  1.2 => It's OK.

3. Set this IO as High-Z , the voltage of output  is  about 2V => I don't know why? I expect it should be 3.3V. it looks like there is a circuit loop to pull down the voltage. I need it keeps in 3.3V.

4. Set this IO as input, the voltage of output  is  about 2V =>  I don't know why? Should it  be 3.3V,too?

I stuck at this problem many days, Is anyone able to help me? Thanks a lot.

 

BR,

Eddie

 

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Advisor
Advisor
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Registered: ‎04-26-2015

@b108463 I'm surprised that worked, at least for any more than a couple of minutes. If you drive 3.3V onto a pin then that's going to forward-bias the protection diodes and give you something that looks a lot like a short to VCCO. Then it's a question of whether the 3.3V regulator, the 1.2V regulator, or the diode gives up first (most likely the diode).

 

Perhaps the Intel/Altera FPGAs have a different I/O layout, although I'd be a bit surprised. The standard design for an I/O pin has a transistor that pulls down to GND and a transistor that pulls up to VCCO. There's no capability to actively pull down to VCCO, which is what it would need to do here (pulling the 3.3V pull-up down). There are the protection diodes, of course, that pull down to around VCCO + 0.7V, but they're permanently enabled.

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Newbie
Newbie
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Registered: ‎05-30-2011

update information:

Our NEXYS Video board (xc7a200t-1SBG484C) adds with Xilinx FMC XM105 Debug Card , the IO FMC_LA02_P connects to another board  with pull-up resistor to 3.3V. 

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Newbie
Newbie
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Registered: ‎05-30-2011

update again,

  It seems the same discussion in here. Should I set the FMC_LA02_P as open-drain IO? Thanks.

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Artix-7-Hi-Z-pullup-down/td-p/651238

 

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Newbie
Newbie
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Registered: ‎05-30-2011

IO_question.JPG

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Advisor
Advisor
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Registered: ‎04-26-2015

@b108463 I suggest you read the Artix 7 datasheet, especially the first page (Absolute Maximum Ratings). Specifically, maximum input voltage to an I/O pin is VCCO + 0.65. In your case, with VCCO = 1.2V, the limit is 1.85V. You may have already done permanent damage to the chip by putting 2V in there.

 

I expect it's being held down by internal diodes, which exist to prevent people doing exactly what you're trying to do...

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Newbie
Newbie
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Registered: ‎05-30-2011

Really!!! Because we ever did the same task with other(A) FPGA board.  (the IO is 1.5V) 

Maybe we need to think about other way.Thanks for your suggestion.

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Advisor
Advisor
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Registered: ‎04-26-2015

@b108463 I'm surprised that worked, at least for any more than a couple of minutes. If you drive 3.3V onto a pin then that's going to forward-bias the protection diodes and give you something that looks a lot like a short to VCCO. Then it's a question of whether the 3.3V regulator, the 1.2V regulator, or the diode gives up first (most likely the diode).

 

Perhaps the Intel/Altera FPGAs have a different I/O layout, although I'd be a bit surprised. The standard design for an I/O pin has a transistor that pulls down to GND and a transistor that pulls up to VCCO. There's no capability to actively pull down to VCCO, which is what it would need to do here (pulling the 3.3V pull-up down). There are the protection diodes, of course, that pull down to around VCCO + 0.7V, but they're permanently enabled.

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Newbie
Newbie
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Registered: ‎05-30-2011

Hi,

  You are right, I think the protection diode is work, so the voltage is always limited in about 2V.

About other FPGA board, I think maybe there is special design on the board.  Thanks  again.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

Interesting discussion.

I can't speak to the other guys parts... But in my experience, the I/O clamp diodes (ESD protection circuits) are easily overlooked. I believe the only family from us that didn't have them on Vcco was the Spartan-6 floating n-well design. 

If you are looking for more background on these, you might find these to be interesting reading:

https://www.xilinx.com/support/documentation/application_notes/xapp1311-hot-swapping-fpgas.pdf (Hot Swapping with FPGAs Application Note)
http://www.xilinx.com/support/documentation/application_notes/xapp251.pdf (Hot-Swapping Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5 Devices)

People often think of this a "hot-swap issue" (as evidenced by the titles above too), but I argue it is also an "adjacent interface power sequencing issue" consideration - and more.

Cheers,

bt

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Registered: ‎01-22-2015

@barriet 

Interesting discussion.   ...but I argue it is also an "adjacent interface power sequencing issue" consideration - and more.

Thank you for joining the discussion! 

Perhaps we can further discuss the simple pullup resistor problem of this post   -  without getting anyone into trouble?

The size of the pullup resistor was not mentioned.  However, Table 2 of the datasheet for many Xilinx FPGAs gives a specification for Iin (max current thru forward biased clamp diode).  So, if the pullup resistor limited the current (from the 3.3V supply) through the IO pin clamp diode to less than Iin under all conditions (eg. FPGA VCCO powered or unpowered), was the FPGA IO pin still in danger of being damaged?

Similarly, Table 1 of datasheets gives a specification for IO Vin (typicall a max of (VCCO + 0.55V)).  Do you think the Vin and Iin specifications could be combined into a more meaningful specification?  -something like, "If applied Vin exceeds (VCCO + 0.55V) then you must limit current into the FPGA IO pin to less than Iin".   

Many thanks,
Mark

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