05-17-2018 06:47 AM
While working on this board, due to voltage (2.5V and 1.2V ) rail shorted inside the FPGA this board stopped working. So we removed the non-working part and replaced with new FPGA on this same board, part mounted on this board is with the same part number as earlier(P/N: XC3SD3400A-4FGG676C) but only date code(1701) is new, as we procured this part recently.
FYI.. recently we procured this part 10qty and mounted on 10 non-working board where FPGA chip is faulty.
when we try to program FPGA, we could able to program on only 3 boards successfully out of 10. Remaining 7 boards are not programmable and the error message is same on all the 7 non-working boards. i.e...
The idcode read from the device does not match the idcode in the bsdl File.
INFO:iMPACT:1578 - '1': Device IDCODE : 00001111111111111111111111111110
INFO:iMPACT:1579 - '1': Expected IDCODE: 00000011100001001110000010010011
Initially, I doubted the Assembly issue on this 7 boards where there might be a chance of FPGA not being soldered properly on the board.
But, when I probed all JTAG signal lines and tried reading JTAG signal by performing Get Device ID details with help of impact V14.7 tool, I observed all JTAG lines are toggling. If the FPGA is not mounted correctly on this board, I should not see any one of the TDI/TDO/TMS/TCK line toggling.
I just collected JTAG signal data using a scope on both the Working and non-working board while Device ID ( Get Device ID) is getting read by impact V14.7 tool.
for your reference here i have attached Waveforms image here collected on the non-working board where i am not able to program FPGA (P/N: XC3SD3400A-4FGG676C, date code is 1701) and facing the Device ID code read issue as mentioned above.
I also attached Waveforms image here collected on the board where i am able to program FPGA (P/N: XC3SD3400A-4FGG676C, date code is 1701) successfully.
Part i am using is a SPARTAN 3A : P/N: XC3SD3400A-4FGG676C
Request to let us know ur suggestions and help us to fix this issue ASAP. in case if i need to edit BSDL file, let me know the procedure to edit BSDL file to match with expected Device ID to program FPGA successfully
Your help and suggestions are appreciated :).
05-17-2018 09:19 AM
Check the pin PUDC_B. It needs to be grounded so that you have internal pullup resistors on the JTAG pins... in the waveform, it looks like the bad board has no pullup on the TDO signal. Does your board use external pullup resistors on TDO? If not, try adding a 5K pullup and seeing if this helps.
05-17-2018 11:14 AM
Thanks for your reply...
May I know how to check the pin PUDC_B?
Yes, you are correct, there are no pull-up resistors on both the boards (Good and bad board)to any of the JTAG signals.
Surely I will add 5K pull-up to TDO signal and try to program and get back to you.
05-17-2018 11:40 AM
Check your board schematic for the PUDC_B pin. It should be grounded. If not, then it's a design error, since you don't have pullup resistors on the JTAG pins.
05-18-2018 05:12 AM - edited 05-18-2018 05:27 AM
Hi Xilinx team,
Currently, PUDC_B pi is not connected to GND or VCC... I added 5K pullup on the Jtag signal externally on my board, still, I face the same issue. Please see attached image.
Now I could not doubt on schematic design issue or soldering issue.
we design this boards and were using it from last 5 years and mounted new FPGA chip(Spartan3A) on the some of these board earlier, we didn't find this kind issue last year.
With the same confidence i replaced new FPGA part on non-working boards, unfortunately, I am facing idcode issue.
Does this FPGA had incorrect ID code. Is it possible?
We were seeking for help from Xilinx team to resolve this issue soon...
05-18-2018 09:44 AM
05-18-2018 10:55 AM - edited 05-18-2018 10:58 AM
Thank You for your reply...
Yes, i studied about PUDC_B pin in Spartan3A data sheet... 5 years ago we designed more than 100 boards with SPARTAN-3A where PUDC_B pin floating....we could not face any issues while programming FPGA earlier.
But after i mount new FPGA on the board inplace of not working FPGA. I am facing issues while programming. I really don't doubt on our board design.
In our design PUDC_B pin open, So on our board, we added 5K external Pull-up on this JTAG Signal, this is similar to the state of JTAG GPIO in the FPGA if i connect the PUDC_B pin to GND. Please confirm.
Moreover, PUDC_B pin in 7 series or Zynq devices should not left open.... I am using SPART-3A FPGA.
Request to suggest us in case we can fix this issue by editing BSDL file with Expected IDcode.
05-18-2018 11:16 AM - edited 05-18-2018 11:20 AM
After doing some reading on PUDC_B, I don't think it's important... The only other explanation that I can think of is that you might have clock ringing on the TCK signal. Check for this by creating a snubber circuit with a 1 nF capacitor in series with a 100 ohm resistor, then attaching this to the furthest point of TCK from the JTAG connector. The resistor goes to GND, and the capacitor to TCK. If the board suddenly starts working, then clock ringing is the problem.
Changing the BSDL file won't help at all. These bad boards are returning the wrong ID code because there's a physical problem on the board.