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Explorer
Explorer
3,281 Views
Registered: ‎05-14-2015

To configure Zynq ultrascale+ PL part

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How many ways do we have to configure PL part of a Zynq ultrascale+? 

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Xilinx Employee
Xilinx Employee
5,478 Views
Registered: ‎08-02-2007

hi,

 

refer to the blog which explains the ways to program PL in Zynq.

https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-195-Using-the-DevC-PCAP/ba-p/766102

 

-hs

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Explorer
Explorer
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Registered: ‎05-14-2015
Add one more question:
Does the PL of this device has the traditional configuration method like pure FPGA device(eg. Kintex ultrascal )? Or, the configuration of PL has to be done by PS part through PCAP(processor configuration access port)?
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Xilinx Employee
Xilinx Employee
5,479 Views
Registered: ‎08-02-2007

hi,

 

refer to the blog which explains the ways to program PL in Zynq.

https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-195-Using-the-DevC-PCAP/ba-p/766102

 

-hs

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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View solution in original post