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Participant
Participant
354 Views
Registered: ‎05-17-2020

UART Lite 2.0 interface port assignment

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Hello.

I'd like to assign the uartlite RX, TX pin to J4_G30, J4_G31 on the ZCU102 board.

cap.JPG

The J4 I mentioned is located at 32.

And my Vivado Design is as shown in the picture below.

image.png

 

 

How can I assign the Uartlite rx, tx pins to ZCU102 board?

Please let me know the details.

 

 

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Xilinx Employee
Xilinx Employee
290 Views
Registered: ‎02-14-2014

Hi @JM_Park ,

There can be several methods to accomplish this. Best bet among them is by adding new constraint file to your design which will override the existing pin location and iostandard constraints generated by axi_uartlite IP. You simply need to create new constraint file uart_constr.xdc and have below constraints in it (Assuming that W12 is rxd and W11 is txd) -

set_property PACKAGE_PIN W12 [get_ports uart2_pl_rxd]
set_property PACKAGE_PIN W11 [get_ports uart2_pl_txd]
set_property IOSTANDARD LVCMOS18 [get_ports uart2_pl_rxd]
set_property IOSTANDARD LVCMOS18 [get_ports uart2_pl_txd]
Regards,
Ashish
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Xilinx Employee
Xilinx Employee
291 Views
Registered: ‎02-14-2014

Hi @JM_Park ,

There can be several methods to accomplish this. Best bet among them is by adding new constraint file to your design which will override the existing pin location and iostandard constraints generated by axi_uartlite IP. You simply need to create new constraint file uart_constr.xdc and have below constraints in it (Assuming that W12 is rxd and W11 is txd) -

set_property PACKAGE_PIN W12 [get_ports uart2_pl_rxd]
set_property PACKAGE_PIN W11 [get_ports uart2_pl_txd]
set_property IOSTANDARD LVCMOS18 [get_ports uart2_pl_rxd]
set_property IOSTANDARD LVCMOS18 [get_ports uart2_pl_txd]
Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

Participant
Participant
267 Views
Registered: ‎05-17-2020

Hi, @ashishd 

Thank you for your reply.

There are several methods as you said, and I solved this problem with a method a little different from yours.

 

1. I entered Open RTL Analysis located left side on Vivado window, and I modified the uart2_pl_rxd and uart2_pl_txd to W12 and W11.

2. The modified things are saved to new xdc file when I exit the RTL Analysis window.

3. I checked the xdc file and it is perfectly same as your xdc file contents you said.

 

 

Finally It works well now. Although, I didn't use your proposed method, but I can verify my method with yours.

Thank you.

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