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mrawson0000
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Registered: ‎05-30-2018

Ultrascale vs Virtex PAR Implementation of Constants

I recently stumbled upon this document showing that Virtex architectures would implement constants by connecting them to unused I/O keeper circuits.

 

See page 21 of https://www.xilinx.com/support/documentation/application_notes/xapp197.pdf

or See page 64 of https://www.xilinx.com/support/documentation/user_guides/ug156-tmrtool.pdf

or https://nepp.nasa.gov/mapld_2008/presentations/w/02%20-%20Quinn_Heather_mapld08_pres_1.pdf

 

I tried to see if this practice is still used in Ultrascale FPGAs, but I couldn't find any information on it.

 

Keeper circuits are still used and can be instantiated, but no information on if they are used for constants.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug974-vivado-ultrascale-libraries.pdf

 

Would love to know! Thanks so much!

Mason

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allanherriman
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Registered: ‎01-08-2012

The term "keeper" is used for two distinct things here, and you seem to be confusing them.

 

The keeper referred to in xapp197 and UG156 is used inside the FPGA fabric on the unconnected inputs of LUTs, etc.  It's a "half latch" used to stop those unconnected inputs flapping about in the breeze.  There are also some radiation tolerance issues (since the keeper may flip in a way that can't (easily) be detected, possibly changing the functionality of the design).

 

The keeper referred to in UG974 is a configuration of the IO buffer weak pullup and pulldowns.  It only applies to IO pins.  It's not really related to the other type of keeper at all.

 

 

That said, I don't know if the first type of keeper is used inside Ultrascale.  I have only seen documentation that says they are used up to Virtex5.

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