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Visitor tomfarmer1
Visitor
1,444 Views
Registered: ‎11-09-2018

Unable to connect to hardware target in Vivado 2018.2.2

I am unable to connect to my target device using a DLC10 using Vivado 2018.2.2 (64 bit) on my local Windows 7 PC.  The target is an Artix-7 XC7A50T FGG484.

Windows Device Manager does see the DLC10 as a "Programming cables" | "Xilinx USB cable".

The device M0 and M2 are pulled high while M1 is pulled low.  The TDO, TDI, TCK and TMS signals are connected directly from the connector, used by the ribbon cable on the DLC10, to the pins on the device; there are no external pull-up/pull-down resistors.  The light on the DLC10 is green.

When I click on "Open Hardware Manager" the Hardware manager comes up.  It reports unconnected and "No hardware target is open". 

If I then click on "Open target" and select "Open New Target", the wizard starts up.  On the Hardware Server Settings I select Connect to Local server and click Next, the Select Hardware Target window appears but the Hardware Targets says "No target" and Hardware Devices says "No device".  The Hardware server is shown as localhost:3121.

Suggestions?????

 

 

 

 

 

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7 Replies
Xilinx Employee
Xilinx Employee
1,419 Views
Registered: ‎08-10-2008

回复: Unable to connect to hardware target in Vivado 2018.2.2

Hi tom,

This should be a hardware connection issue. How many devices are there in the JTAG chain along with the 7A part? If you have other devices and you have jumpers to bypass, try to leave only A7 in the chain.
Next, probe the connections on the board between each, like cable-jumpers, jumpers to device, make sure the the connections are good and the power rails are in the right range.

Ivy
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Visitor tomfarmer1
Visitor
1,406 Views
Registered: ‎11-09-2018

回复: Unable to connect to hardware target in Vivado 2018.2.2

There are no other devices in the JTAG chain.  The connection is literally the 14-pin ribbon cable to a 14 pin connector on my board; the 4 signals are connected to the chip via inner-layer routing to a via under the BGA.

Probing the connector on my board, the TMS, TCK, TDI, and TDO pins all are fixed at +3.3V.

As for the PCB traces, the connector on the target board pin 2 is connected to +3.3V and the odd numbered pins are connected to ground.  On the board:  connector Pin 4 (TMS) is connected to device T13; connector Pin 6 (TCK) is connected to device pin V12; connector Pin 8 (TDO) is connected to device pin U13; connector Pin 10 (TDI) is connected to device R13.

 

 

 

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Visitor tomfarmer1
Visitor
1,397 Views
Registered: ‎11-09-2018

回复: Unable to connect to hardware target in Vivado 2018.2.2

Not totally sure how I got to this point, but I think I solved the problem by poking around...

In the hardware pane, I right-clicked on "localhost" and then selected "Create SVF target."  I was then able to give something a name (don't remember what) and select the device on my board.  It then appeared in the "Device Chain" pane.  I went to the SVF operations below it and created a "Program device" operation.

I suspect the root cause is that the XILINX documentation UG908 (v2018.2) page ~27 and elsewhere were written by someone who already had an *.svf file created.  Starting with a blank system, as I did , meant that the .svf file did not exist.  I suggest Xilinx update the documentation to describe how to create the *.svf file.

 

 

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Visitor tomfarmer1
Visitor
1,388 Views
Registered: ‎11-09-2018

回复: Unable to connect to hardware target in Vivado 2018.2.2

Well, the device apparently is not getting programmed even though it is reported to be programed in Vivado.

Clicking on Export SVF creates a .svf file, but the TCL console indicates that it is executing a program_hw_devices successfully.  The hardware pane shows the (xc7a50t_0(0) part as "programmed."  With the part selected in the Hardware pane, the Hardware Device Properties pane does not look much like Figure 4-7 of UG908(v2018.2) {page 31}.  While the PARTIAL_PROBES, PROBES, and PROGRAM lines appear, there is no REGISTER line.  I am pretty sure the device is not programmed because the chip pins appear to be floating HIGH even though my design has an observable pin that should be LOW. 

Another data point:  The Program Device text in the Flow Navigator | PROGRAM AND DEBUG | Open Hardware Manager is still greyed out and nothing happens when I click on it.

Perhaps also telling, I get the exact same response in Vivado if I disconnect the DLC10 from the target completely and execute the same steps in Hardware Manager....

 

Suggestions???

 

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Xilinx Employee
Xilinx Employee
1,379 Views
Registered: ‎03-07-2018

回复: Unable to connect to hardware target in Vivado 2018.2.2

Hi @tomfarmer1

Did you tried uninstalling and installing of cable driver as per https://www.xilinx.com/support/answers/54381.html ?

 

Regards,
Bhushan

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Visitor tomfarmer1
Visitor
1,336 Views
Registered: ‎11-09-2018

回复: Unable to connect to hardware target in Vivado 2018.2.2

I tried uninstalling and reinstalling the drivers multiple times without success. 

We are able to configure the FPGA via an on-board microprocessor using a non-JTAG interface on the FPGA.  We have multiple boards and all exhibit the issue so I don't think it is a board workmanship issue.  Given that the chip works fine without using the JTAG interface, we have decided not to invest more time chasing down this issue.

Bottom line -- we never were able to resolve the problem but worked around it.  It is possible the download cable was defective; it was brand new but we never tried using it on another design.....

 

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Visitor chainastole
Visitor
280 Views
Registered: ‎07-26-2019

Re: Unable to connect to hardware target in Vivado 2018.2.2

I have the similar problem described in https://forums.xilinx.com/t5/Implementation/Unable-to-connect-to-hardware-target-in-Vivado-2019-1-in-Windows/m-p/1008992#M25719. Wnated to check maybe you nevertheless finally succeeded to solve?

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