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Observer
Observer
9,969 Views
Registered: ‎07-23-2014

Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

Hello,

 

I made an RTL project for xc7z010clg400-1 Board and was able to load the bitstream. However when i tried to make an .mcs file for the onboard Spasion S25FL256S 256 Mbits qspi x4 single FLash, it gave an error about SPI Buswidth mismatch.

 

write_cfgmem -format mcs -interface spix4 -size 32 -loadbit "up 0x0 C:/Vivado/csa_zynq_ps_brams_ila/csa_zynq_ps.runs/impl_1/System_wrapper.bit" -file design.mcs

...
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile C:/Vivado/csa_zynq_ps_brams_ila/csa_zynq_ps.runs/impl_1/System_wrapper.bit
ERROR: [Vivado 12-3735] SPI_BUSWIDTH property is set to "1" on bitfile C:/Vivado/csa_zynq_ps_brams_ila/csa_zynq_ps.runs/impl_1/System_wrapper.bit. This property has to be set to "4" to generate a configuration memory file for the SPIX4 interface. Please ensure that a valid value has been set for the property BITSTREAM.Config.SPI_buswidth and rerun this command.
ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors.

 

If i try to change the SPI bus width using

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

 

It gives this error about some hardware probe object
ERROR: [Labtoolstcl 44-151] This Tcl property command is only supported with a hw_probe object.

 

Finally if I use 

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [lindex [get_hw_devices] 1]

 

then it says it cannot change a readonly proprty...
WARNING: [Common 17-107] Cannot change read-only property 'BITSTREAM.CONFIG.SPI_BUSWIDTH'.

 

Can anyone please help me with this. Flash configuration file generation used to be very simple and easy with iMPACT.

Why is this Vivado so messed up.

 

Note: I am not getting the "configuration Options" tab available in "Tools->Edit Device prperties"  as described in UG908.

I have read UG908, UG935, UG936 all for this problem but no use.

 

Can anyone help on this? Or has anyone faced similar problem?

 

 

Best Regards,

Asrar

 

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Xilinx Employee
Xilinx Employee
9,965 Views
Registered: ‎02-16-2014

Re: Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

Hi,

 

To correctly generate BIN or MCS in SPIx4 or SPIx2 mode, bitstream property "SPI_BUSWIDTH" should have been set properly in the bit file:

set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
 
One way is to add the Tcl command into .xdc and rerun implementation.
 
Another more convenient way without rerunning is to open the implemented design, and put the following commands in Tcl console successively:
    1.set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
    2.write_bitstream xxx.bit (make sure do not click "Generate Bitstream" button instead)
    3.write_cfgmem -format mcs -interface SPIx4 -size xxx -loadbit "up 0x0 xxx.bit" -file xxx.mcs
 
The mcs file should be generated sucessfully.
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Observer
Observer
9,949 Views
Registered: ‎07-23-2014

Re: Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

Hello Manushka,

 

So, writing that "set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]"  line in xdc file did not work.

Again got the same error after re-implementing, generating bitsream and running write_cfgmem

 

ERROR: [Vivado 12-3735] SPI_BUSWIDTH property is set to "1" on bitfile C:/Vivado/csa_zynq_ps/csa_zynq_ps.runs/impl_1/System_wrapper.bit. This property has to be set to "4" to generate a configuration memory file for the SPIX4 interface. Please ensure that a valid value has been set for the property BITSTREAM.Config.SPI_buswidth and rerun this command.
ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors.

 

As for your second alternative option, I already mentioned in the actual post that

"set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]"  in TCL console gives the following ERROR

ERROR: [Labtoolstcl 44-151] This Tcl property command is only supported with a hw_probe object.

 

Any other options or suggestions please?

 

Regards

Asrar

 

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Observer
Observer
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Registered: ‎07-23-2014

Re: Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

and by the way,

 

Upon inserting the set_property command in xdc file I gotthis critical warning.

 

[Netlist 29-177] Cannot set property 'BITSTREAM.Config.SPI_buswidth' because the property does not exist. [C:/Vivado/csa_zynq_ps/csa_zynq_ps.srcs/constrs_1/new/System_wrapper.xdc:3]
Resolution: Create this property using create_property command before setting it.

 

How is it possible that the property does not even exist???

 

Does anyone from Xilinx have any info or solution to this? I'm stuck in the middle of a project timeline.

 

Thanks

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Xilinx Employee
Xilinx Employee
9,809 Views
Registered: ‎04-16-2012

Re: Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

Hello,

 

I am able to generate bitstream with the following xdc constraint in the XDC file.

 

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

 

I am using Vivado 2014.2

 

Thanks,

Vinay

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5,586 Views
Registered: ‎03-18-2016

Re: Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

Hi, there,

I think you have missed the step "1st - open the implement design" and then "2nd - type the 3 tcl commands in the tcl console".

I also met the same problems as you today. After read the upper answer by the Xilinx emplyee, I tried as his suggests and get the correct mcs file successfully.

May my answer is not too lateeeee...(Today is already 12/20/2016)

Best Regards,

CrazyWind 

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Visitor
Visitor
5,334 Views
Registered: ‎01-26-2017

Re: Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

hi everybody 

i ' m using vivado 2016.4_7 and zedboard.

 

i could not create mcs file because of error that is  " SPI_BUSWIDTH property is set to "1" on bitfile C:/*****/led_yakma.bit. This property has to be set to "4" to generate a configuration memory file for the SPIX4 interface. Please ensure that a valid value has been set for the property BITSTREAM.Config.SPI_buswidth and rerun this command."

 

Tools>Edit device properties > Configuration 

 

i couldn't find SPI configuration settings in vivado. 

 

then 

 

i write "set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design ]" into TCL console  and i added same script to XDC file  but it returned this error "ERROR: [Netlist 29-177] Cannot set property 'BITSTREAM.Config.SPI_BUSWIDTH' because the property does not exist.
Resolution: Create this property using create_property command before setting it." 

 

because of i couldn't this step , i couldn't start  other steps.

 

how can i change spi_bus_width with vivado ide or TCL console ?

 

thanks advance 

 

 

 

 

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Observer
Observer
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Registered: ‎06-22-2017

Re: Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

Hello,

Did you find a solution? I am running into the same issue.

Thanks,
raphael
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Observer
Observer
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Registered: ‎08-01-2018

Re: Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

Still in Vivado 2019.2, I am not able to find where this property is supposed to be set. This error message is worthless because the bit file does not say how to set properties on a bit file: 

[Writecfgmem 68-20] SPI_BUSWIDTH property is set to "1" on bitfile design.bit. This property has to be set to "4" to generate a configuration memory file for the SPIX4 interface. Please ensure that a valid value has been set for the property BITSTREAM.Config.SPI_buswidth and rerun this command.

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Observer
Observer
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Registered: ‎08-01-2018

Re: Unable to create .mcs file using Vivado 2014.2 , SPI BUS WIDTH MISMATCH

I was able to locate it, although I was never able to find an accurate description of where to find it.

Anyway, open the implemented design, then right click on "Generate Bitstream" in the Flow Navigator and select Bitstream Settings... At the top of the window that pops up, there is a message with an information icon, even though it is not an informational message. It is not telling you to configure additional bitstream settings on this page; it is actually a link that allows you to set bitstream settings not shown on this page. Click on that info message that is not an info message and you get another pop up window.

There is a lot of stuff that can be configured in that pop up. The SPI bus width is under "Configuration" on the left and under "SPI Configuration" on the right. 

After that, be sure to save the implemented design, even though you didn't edit the implemented design. You edited the bitstream generation settings which are not part of the implemented design on the left in the Flow Navigator, but for some reason it has changed the implemented design.

And even though you are setting something that just changes the way that the bitfile is produced, Vivado wants to reimplement the entire design. *sigh*

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