08-16-2019 01:06 PM
When trying to program an ISSI flash part using Vivado 2018.3 hardware manager, I get the following error:
[Labtools 27-2251] Unable to read device properties. Please make sure that the proper configuration memory part is selected.
After scoping the communication lines, we found out that the FPGA sends the right clock signal (3MHz) and it activate CS signal (it goes to 0 since it is active low) but there is no communication activity on DQ0 or DQ1. Both signals read 0 volt. Attached is a scope screenshot (C1: CLK, C2: DQ0 and C3: CSbar). Not sure why the FPGA is NOT sending data and I could you some help here. Below is some info about my design:
Configration voltage: 3.3V
Configration rate: 3MHz
Configration width: 4xSPI
And here is the XDC constraints related to the configration settings
set_property BITSTREAM.CONFIG.CONFIGRATE 3 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
08-18-2019 08:17 PM
1. Did you correctly select IS25LP016D in GUI?
2. Is there any other warning issued during the programming process?
3. What if you generate a x1 file and try to program it? Please check if this is successful.
08-19-2019 02:47 PM
08-19-2019 06:04 PM
Then try to erase the flash, does same error message occur? If so, check the schematic first and see if there is some wrong connection between FPGA and SPI.
You can use this vivado and cable to download bit to fpga right? Did you encoutner any SI/CRC issue?
08-20-2019 12:01 AM
We get the same error when erasing the flash.
Schematic was checked by both xilinx and ISSI.
We can use both vivado and xilinx SDK to download the bit file and run the code but we can't program use the flash.
08-22-2019 02:35 PM
08-22-2019 02:49 PM
Happy to share the full schematic if I can get a private email address. For now I attached screenshots of the connections in question. Let me know if you see anything you don't like. This issue happned on all three boards we tested so far.
09-12-2019 11:09 AM
To update this project:
Tried on both 2018.3 and 2019.1 - no change
Customer loaded sample bitstream in FPGA to toggle MOSI pin to verify it is not shorted. This test was successful.
Customer shipped platform to FAE to recreate error. FAE witnessed similar results.
QUESTION: Has Xilinx confirmed the IS25LP016 can program a Spartan 7 device? What device/tool combinations were used in the validation process?
Are there other low level commands/mechanisms for Vivado/HW manager to bit bang or interrogate the FLASH? We do not see data out of MOSI line.
09-20-2019 09:19 AM