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rick.b.brown
Visitor
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Registered: ‎08-27-2010

Unable to program configuration SPIx1 flash via Artix-7 (XC7A50T)

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We're experiencing a problem where we are unable to program the configuration flash.

 

FPGA P/N: XC7A50T-2CSG325C

Flash P/N: S25FL128SAGBHIA10  (Spansion, 256k sector)

Synthesis Tool: Vivado 2015.1

Lab Tool: Vivado 2016.1

 

Vivado inconsitently reports both passing and failed blank checks.  Vivado always reports program verify as unsuccessful.

We've attempted to program flash without verifying; however, the FPGA failed to boot from flash.  A viado log file is attached.

 

Using an external analyzer, we were able to read and write to the flash device.

 

While exploring timing from the FPGA to the device, we notice a couple oddities we were not expecting (see attached scope shot):

 

1) MOSI appears to change on the rising edge of CCLK; contrary to note 8 on Figure 2-12 and as shown in Figure 2-13 of the configuration user's guide.  (We tried this with the spi_edge_falling set to yes and no with no apparent change to this timing relationship)

 

2) We've set the ConfigRate option to 3MHz; however, the CCLK frequency as measured is not (~7MHz) 

 

Any ideas?

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6MHz_SPI_Timing.png
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rick.b.brown
Visitor
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Registered: ‎08-27-2010

This was ultimately resolved via the service request process.  Root cause is VCCBRAM is out of spec due to design error where these pins are connected to the incorrect voltage net.

 

Two things we learned which may be helpful to others:

1) SPI interface timing during the indirect programming process is different than the documented timing during FPGA configuration.

2) BRAM is used to for buffering data between clock domains during the indirect programming process.

View solution in original post

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aher
Xilinx Employee
Xilinx Employee
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Registered: ‎07-21-2014
Hi,

Can you please share the schematic here?
Please attach configuration properties that you have set in xdc file and command you have used to generate mcs file along with .prm

-Shreyas
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rick.b.brown
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Registered: ‎08-27-2010

Hi Shreyas,

 

I have attached the schematic sections pertaining to the configuration portions. Please see attached.

 

Here’s command to generate MCS:

write_cfgmem  -format mcs -size 16 -interface SPIx1 -loadbit "up 0x00000000 C:/SpiCheckout.bit " -file "C:/SpiCheckout.mcs"

 

Here’s the XDC constraints for “master SPI” configuration (created by “Edit Device Properties”)

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]

set_property BITSTREAM.CONFIG.SPI_FALL_EDGE NO [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

set_property CONFIG_MODE SPIx1 [current_design]

 

set_property BITSTREAM.CONFIG.CONFIGRATE 3 [current_design]

set_property CONFIG_VOLTAGE 2.5 [current_design]

set_property CFGBVS VCCO [current_design]

 

Prom file is also attached. (please remove the extra .txt, for some reason, the UI kept stripping off the attachment as non-text/plain)

 

--Rick

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rick.b.brown
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Registered: ‎08-27-2010

Shreyas,

 

Any updates? 

 

--Rick

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rick.b.brown
Visitor
Visitor
14,232 Views
Registered: ‎08-27-2010

This was ultimately resolved via the service request process.  Root cause is VCCBRAM is out of spec due to design error where these pins are connected to the incorrect voltage net.

 

Two things we learned which may be helpful to others:

1) SPI interface timing during the indirect programming process is different than the documented timing during FPGA configuration.

2) BRAM is used to for buffering data between clock domains during the indirect programming process.

View solution in original post

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