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Visitor _fenrir
Registered: ‎02-18-2019

Understanding ICAP

Hi, I'm trying to get ready to use the ICAPE3 interface in UltraScale and I'm trying to sort everything out in my head first. One thing I can't grasp in the documentation, I don't fully understand it and I have a request for explanation - namely, how is the ICAPE3 informed that there is no more configuration data to load? Does it just work on the principle that I have to load the entire configuration file through this port in one sequence? And I understand that through ICAPE3 I should first upload the configuration file with the clearing configuration (because it is the UltraScale family), and then the file with the target functionality? Whole bit files are uploaded, as with JTAG configuration, without any modifications? Please make it clear for me.
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Xilinx Employee
Xilinx Employee
Registered: ‎08-25-2010

回复: Understanding ICAP

Hi @_fenrir,


The end of a BIT(or partial BIT) file has a DESYNCH word (0000000D) that informs the configuration engine that the BIT file has been completely delivered. Clearing bit(Ultrascale) must be sent to configuration engine before the next partial configuation bit same as JTAG, without any modification.

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