UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor _fenrir
Visitor
409 Views
Registered: ‎02-18-2019

Understanding ICAP

Hi, I'm trying to get ready to use the ICAPE3 interface in UltraScale and I'm trying to sort everything out in my head first. One thing I can't grasp in the documentation, I don't fully understand it and I have a request for explanation - namely, how is the ICAPE3 informed that there is no more configuration data to load? Does it just work on the principle that I have to load the entire configuration file through this port in one sequence? And I understand that through ICAPE3 I should first upload the configuration file with the clearing configuration (because it is the UltraScale family), and then the file with the target functionality? Whole bit files are uploaded, as with JTAG configuration, without any modifications? Please make it clear for me.
Tags (1)
0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
379 Views
Registered: ‎08-25-2010

回复: Understanding ICAP

Hi @_fenrir,

 

The end of a BIT(or partial BIT) file has a DESYNCH word (0000000D) that informs the configuration engine that the BIT file has been completely delivered. Clearing bit(Ultrascale) must be sent to configuration engine before the next partial configuation bit same as JTAG, without any modification.

Thanks
Simon
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------