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Visitor roiaibester
Visitor
193 Views
Registered: ‎07-02-2019

Using flash for both configuration (bit file) and for NVM (for read write)

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Hi, 

I am using VCU118 Evaluation Board REV2, and I am trying to use the Micron dual MT25QU01GBB8ESF serial NOR flash.

initialy I followed ug908-vivado-programming-debugging guild to have the bitstream auto load from the flash device, and program the FPGA.

That work very well.

Now I'd like to also use the Flash device as a non volatile memory (basically for FW drivers).

So after programming the FPGA, I have an SPI master that is generating SPI protocol commands.

I tested my design with simulation (VCS) with Micron's BFM (same device as VCU118 has), and its woking well.

I generated the MCS file with vivado, and also read it back from the flash (with vivado GUI), and the data on the flash seems to be OK.

But when I try to read it with my design all I get are FFFF's.

I tried two approches:

1. I tried connecting directly to bank65 with XDC constrains:

# SPI Master
set_property IOSTANDARD LVCMOS18 [get_ports sclk_pad ]
set_property IOSTANDARD LVCMOS18 [get_ports ss_0_n_pad]
set_property IOSTANDARD LVCMOS18 [get_ports d0_pad ]
set_property IOSTANDARD LVCMOS18 [get_ports d1_pad ]
set_property IOSTANDARD LVCMOS18 [get_ports d2_pad ]
set_property IOSTANDARD LVCMOS18 [get_ports d3_pad ]

set_property PACKAGE_PIN AL20 [get_ports sclk_pad ]
set_property PACKAGE_PIN BF16 [get_ports ss_0_n_pad]
set_property PACKAGE_PIN AM19 [get_ports d0_pad ]
set_property PACKAGE_PIN AM18 [get_ports d1_pad ]
set_property PACKAGE_PIN AN20 [get_ports d2_pad ]
set_property PACKAGE_PIN AP20 [get_ports d3_pad ]

And the pads d0,d1,d2,d3 are connected at the design with IOBUF:

IOBUF IOBUF_d0
(
 .O (d0_pad_out ), // 1-bit output: Buffer output
 .I (d0_pad_in ), // 1-bit input : Buffer input
 .IO(d0_pad ), // 1-bit inout : Buffer inout (connect directly to top-level port)
 .T (ssi_oe_n[0]) // 1-bit input : 3-state enable input
 );

 

This didnt work...

All I get are FFFF's.

 

2. I tried following xapp1280-us-post-cnfg-flash-startupe3.

I only connected my SPI master to the startupe3 block, and didn't have any SPI constrains at the XDC file:

STARTUPE3 #(
 .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
 .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency (ns) for simulation
 )
 STARTUPE3_inst (
 .CFGCLK (), // 1-bit output: Configuration main clock output
 .CFGMCLK (), // 1-bit output: Configuration internal oscillator clock output
 .DI (rxd ), // 4-bit output: Allow receiving on the D input pin
 .EOS (), // 1-bit output: Active-High output signal indicating the End Of Startup
 .PREQ (), // 1-bit output: PROGRAM request to fabric output
 .DO (txd ), // 4-bit input: Allows control of the D pin output
 .DTS (ssi_oe_n ), // 4-bit input: Allows tristate of the D pin
 .FCSBO (ss_0_n), // 1-bit input: Controls the FCS_B pin for flash access
 .FCSBTS (1'b0), // 1-bit input: Tristate the FCS_B pin
 .GSR (1'b0 ), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port)
 .GTS (1'b0 ), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
 .KEYCLEARB (1'b1 ), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
 .PACK (1'b0 ), // 1-bit input: PROGRAM acknowledge input
 .USRCCLKO (sclk_out), // 1-bit input: User CCLK input
 .USRCCLKTS (1'b0), // 1-bit input: User CCLK 3-state enable input
 .USRDONEO (1'b1), // 1-bit input: User DONE pin output control
 .USRDONETS (1'b1) // 1-bit input: User DONE 3-state enable output
 );

 

Also didnt work...

All I get are FFFF's.

 

So:

1. did I miss anything? 

2. Is there a way to simulate the startupe3 in VCS?

3. Is there a way to simulate the flash access on vivado simulator?

 

 

Thanks,

Roi

 

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Xilinx Employee
Xilinx Employee
53 Views
Registered: ‎06-06-2018

Re: Using flash for both configuration (bit file) and for NVM (for read write)

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Hi @roiaibester ,

Answered through SR.

Regards,
Deepak D N
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Visitor roiaibester
Visitor
168 Views
Registered: ‎07-02-2019

Re: Using flash for both configuration (bit file) and for NVM (for read write)

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Just to clearify -  at the two attempts above to read from the flash, I did not write to the flash the bitsream file for auto programing the FPGA. I only wrote to the flash the data I'd like to read through the FPGA.

I only mentiond it above to show that the programming flow through the SPI works (in a differant case...).

I also have at the XDC file the following (for both cases above): 

set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
 set_property BITSTREAM.CONFIG.CONFIGRATE 31.9 [current_design]
 set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 1 [current_design]
 set_property BITSTREAM.STARTUP.LCK_CYCLE 6 [current_design]
 set_property BITSTREAM.STARTUP.MATCH_CYCLE 6 [current_design]

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Xilinx Employee
Xilinx Employee
54 Views
Registered: ‎06-06-2018

Re: Using flash for both configuration (bit file) and for NVM (for read write)

Jump to solution

Hi @roiaibester ,

Answered through SR.

Regards,
Deepak D N
---------------------------------------------------------------------------
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