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Observer tommyc
Observer
7,147 Views
Registered: ‎01-30-2015

Virtex-6 clock region frame address for SEM error injection

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Hi,

 

i am trying to figure out 'physical frame addressing' for the Virtex-6; specifically if there is any relationship between frame address and clock region.

 

I have created a design in System Generator which incorporates a module that I wish to test as well as a SEM core and some additional modules of my own.  I have modified the design using PlanAhead to seperate the module under test away from the rest of the design. For convenience I allocated one specific clock region to the module under test.

 

Now I want to use the SEM core to inject SEU type errors into that clock region containing the module unter test. The SEM controller user guide gives a breakdown of the 36bit error injection command, showing which bits refer to

 

 

  • Block type
  • half address
  • row address
  • column address
  • minor address
  • word address
  • bit address

but I cannot find any explanation of what these terms actually mean. 

 

Is there a simple relationship between the physical frame address and the clock region? or between the physical frame address and the physical location on the chip?

 

Thanks

Tom

 

(I am using the ML605 evaluation board with ISE 14.7 and running hardware cosimulation through system generator with Matlab 2013b)

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Accepted Solutions
Scholar austin
Scholar
12,803 Views
Registered: ‎02-27-2008

Re: Virtex-6 clock region frame address for SEM error injection

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t,

 

14.7 supports the generation of an essential bit file.

 

That file has ONLY those bits related to the function of the design.

 

There is an app note on creating essential bit files fre different partitions (enhanced essential bits).

 

Our customers use this to test to find the critcal bits (one tha causes a visible functional failure, as most essential bits are masked in space or time, and do not result in error).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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3 Replies
Scholar austin
Scholar
12,804 Views
Registered: ‎02-27-2008

Re: Virtex-6 clock region frame address for SEM error injection

Jump to solution

t,

 

14.7 supports the generation of an essential bit file.

 

That file has ONLY those bits related to the function of the design.

 

There is an app note on creating essential bit files fre different partitions (enhanced essential bits).

 

Our customers use this to test to find the critcal bits (one tha causes a visible functional failure, as most essential bits are masked in space or time, and do not result in error).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer tommyc
Observer
7,114 Views
Registered: ‎01-30-2015

Re: Virtex-6 clock region frame address for SEM error injection

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will the enhanced essential bit file give me the frame addresses for error injection?

 

Also would it allow me to distinguish between the region containing the module under test and the region containing the SEM core?

 

Thanks

 

Tom

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Scholar austin
Scholar
6,934 Views
Registered: ‎02-27-2008

Re: Virtex-6 clock region frame address for SEM error injection

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Yes,

 

By using the essential bit file, you are able to inject errors in just those bits, in order to discover which bits are essential (cause user-visible errors).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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