06-11-2020 10:05 PM
We had to migrate to Asynchronous flash memory due to EOL status of Synchronous flash memory for configuration of Virtex Ultrascale (VU095 device) In this case will the usage of external EMC clock of 90 MHz result in any improvement in configuration and read times.
06-12-2020 02:48 AM
Please refer to Table 47 in UG908(v2019.2) for a list of flash devices that Xilinx supports for use with your Virtex UltraScale device. I suspect that your asynchronous NAND flash is not supported.
When using the synchronous SPI flash devices shown in Table 47, FPGA configuration time will improve if you use the external EMCCLK clock instead of the internal CCLK.
07-27-2020 10:15 PM
Thanks for your reply. I am using an Asynchronous NOR flash memory, which is listed in the supported device in UG908. I would like to know if connecting an External clock EMCCLK will speed up configuration compared to configuration without CCLK in Asynchronous reads.
I have also referred to the latest doc. UG570 which mentions the use of EMCCLK in asynchronous reads.
07-28-2020 03:59 AM
On pages 71-72 of UG570(v1.12), there are calculations that allow you to determine the maximum frequency (ConfigRate) for configuration of your FPGA from asynchronous flash. Some of the numbers that you need for these calculations can be found in the datasheet, DS893, for your VU095 device. Other numbers that you need can be found in the datasheet for your flash part and in the datasheet for your EMCCLK.