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Visitor
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Registered: ‎01-07-2016

Virtex7 Status register read via Slave SelectMAP

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Hi,

In a project I'm working on, there is an external controller connected to a non-volatile memory, which is in charge of configuring a Virtex7 via slave SelectMAP interface. Upon power-up the controller reads the bitstream from the non-volatile memory and writes it to the Virtex7 via slave SelectMAP.

The configuration via the SelectMAP works properly. (Done signal rising and the design is active).

After the Virtex7 is configured, I want to read the Virtex7's status register, using the controller via slave SelectMAP interface. 

I've added to the XDC file the following line:

   set_property BITSTREAM.CONFIG.PERSIST YES [current_design]

   set_property CONFIG_MODE S_SELECTMAP16 [ current_design]

I have implemented the command sequence, according to UG470 table 6.1

Unfortunately, instead of receiving valid data, I get constant 0xD9.

But after I program the exact same bitstream to the Virtex7 via JTAG (done signal rising and the design is active), if I run the exact same command sequence by the controller via slave SelectMAP, I get valid Status register data. 

So I know I'm running the command sequence via SelectMAP properly. 

The erroneous SelectMAP read only happens after the SelectMAP configuration. 

The constant D9 data I read on the SelectMAP may imply DALIGN (Sync word not received). But the exact same command sequence works properly after configuration via JTAG.

Please advise...

Thanks

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Visitor
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Registered: ‎01-07-2016

Figured out what was the problem.

I configured the Virtex7 via SelectMAPx16 and tried to read the Status register via  SelectMAPx8.

I thought that because the bitstream ends with a DESYNC command and the Status register commands sequence begins with the bus width auto detect words, that the configuration controller logic will switch to x8 bus.

It did not. The bus remained x16.

Having changed the Status register read interface to x16, I was able to read properly.

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Moderator
Moderator
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Registered: ‎06-05-2013

Do you see EOS bit high in the status registers after the selectmap programming?

By default done pin goes high in phase -4 and the EOS{end of startup} bit (in status register) goes high in phase 6. 

Read the status registers using JTAG, after selectmap programming. Do you see EOS high? 

If EOS stays low, try to add a few more clocks(after done goes high) to take out the part from the startup cycle. Refer to the AR https://www.xilinx.com/support/answers/42128.html 

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Visitor
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Registered: ‎01-07-2016

Dear hj,

Thanks for your reply.

Per your advice, after configuration via SelectMAP, I've read EOS (bit #4 of Status register) via jtag (vivado tools). It is High.

Any other idea?

BR 

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Highlighted
Visitor
Visitor
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Registered: ‎01-07-2016

Figured out what was the problem.

I configured the Virtex7 via SelectMAPx16 and tried to read the Status register via  SelectMAPx8.

I thought that because the bitstream ends with a DESYNC command and the Status register commands sequence begins with the bus width auto detect words, that the configuration controller logic will switch to x8 bus.

It did not. The bus remained x16.

Having changed the Status register read interface to x16, I was able to read properly.

View solution in original post

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