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anding
Adventurer
Adventurer
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Registered: ‎04-04-2010

Vivado 2017.3 fails to program an MCS file where 2015.4 succeeds

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Hello,

 

I have a .MCS file.  Vivado 2015.4 successfully programs the flash memory and the FPGA powers up OK.  Vivado 2017.3 claims to program the flash memory successfully, but the FPGA does not power up correctly.  Identical .MCS file, the only difference is whether I use the Hardware Manager in 2015.4 (success) or 2017.3 (failure).

 

Any suggestions for next steps would be much appreciated.

 

set_property PROGRAM.ADDRESS_RANGE  {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
set_property PROGRAM.FILES [list "E:/N.I.G.E.-Machine/Board_Nexys4DDR.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
set_property PROGRAM.PRM_FILE {} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
set_property PROGRAM.BLANK_CHECK  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
set_property PROGRAM.ERASE  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
set_property PROGRAM.CFG_PROGRAM  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
set_property PROGRAM.VERIFY  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
set_property PROGRAM.CHECKSUM  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
startgroup 
if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE  [lindex [get_hw_devices xc7a100t_0] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]]]] }  { create_hw_bitstream -hw_device [lindex [get_hw_devices xc7a100t_0] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices xc7a100t_0] 0]]; program_hw_devices [lindex [get_hw_devices xc7a100t_0] 0]; }; 
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a100t_0] 0]]
Mfg ID : 1   Memory Type : 20   Memory Capacity : 18   Device ID 1 : 0   Device ID 2 : 0
Performing Erase Operation...
Erase Operation successful.
Performing Program and Verify Operations...
Program/Verify Operation successful.
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
program_hw_cfgmem: Time (s): cpu = 00:00:02 ; elapsed = 00:01:33 . Memory (MB): peak = 1446.742 ; gain = 0.000
endgroup
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1 Solution

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anding
Adventurer
Adventurer
1,928 Views
Registered: ‎04-04-2010

I have upgraded to 2018.1 and the problem seems to have resolved itself

View solution in original post

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6 Replies
kvasantr
Moderator
Moderator
2,252 Views
Registered: ‎04-12-2017

Hello @anding,

 

What is the difference between timing of programming in both the hardware managers ?

Also what is the difference in functionality of FPGA you are observing ?

 

Please elaborate your issue in detail. 

It will help to debug the issue.

Thank you.

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anding
Adventurer
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Registered: ‎04-04-2010

Thanks for taking a look kvasantr.

 

I should have pointed out that the hardware manager in Vivado 2017.3 is unable to configure the device correctly, irrespective of whether I am taking an old .MCS file that was created with Vivado 2015.4 or a new .MCS file that was created with Vivado 2017.3.  The hardware manager in 2015.4 is able to configure the device correctly with both .MCS files.

 

It's hard to describe the difference in FPGA functionality - as far as the circuit board is concerned the FPGA is simply "inert".  I do not have any debug cores (have not needed them). 

 

Oddly enough Vivado 2017.3's hardware manager can successfully program the FPGA with the .BIT file (either a .BIT file produced by itself or by Vivado 2015.4).  So this seems to be some difficulty with 2017.3 programming .MCS files.

 

I'm not sure I really understood what you meant by "timing of programming"?

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kvasantr
Moderator
Moderator
2,234 Views
Registered: ‎04-12-2017

Hello @anding,

 

By "Configuration timing" I meant time taken by tool to upload the bit stream in the device.

Can you please share the status register values for 2017.3. 

Also share the bitgen settings if possible. 

Also confirm if there is any kind of encryption is used.

 

Here I consider that there is no critical warning observed while implementing the project in tool before generation of bit stream.

Thank you.

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iguo
Xilinx Employee
Xilinx Employee
2,220 Views
Registered: ‎08-10-2008
Hi a,

17.3 reports the MCS file is successfully programmed right? What if you power cycle your board or just pulse PROG_B pin of FPGA? Can 7a start working?
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anding
Adventurer
Adventurer
2,212 Views
Registered: ‎04-04-2010

Configuration timing seemed about the same with either version of Vivado.

 

No encryption

 

Yes 2017.3 reports .MCS successfully programmed.  I always power cycle the board after MCS programming, this was the protocol for the results obtained.

 

I've reverted the project back to 2015.4 at the moment as I had some other issues with 2017.3 - timeout on program launch and time is pressing.  Will report the bitgen and status-register settings later.

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anding
Adventurer
Adventurer
1,929 Views
Registered: ‎04-04-2010

I have upgraded to 2018.1 and the problem seems to have resolved itself

View solution in original post

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