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Visitor
Visitor
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Registered: ‎01-18-2019

What's JTAG input when it is not being used

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First post here. Absolute beginner :)
I am using CPLD ‎XC2C64A.
Everthing works fine on the development board.
Then, I sent the .jed file along with my PCB design to the assembly factory.
When it came back, the CPLD is not working as expected.

I suspect my JTAG interface is not configued correctly.
Are TDI, TDO, TCK, TMS pulling high/low or floated when they are not being used?
If pulling high, do I connect it with resistors?
I googled for a long time, and it seems they need to pull up but not 100% sure.

Thank you.

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Teacher
Teacher
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Registered: ‎07-09-2009
https://www.xilinx.com/support/answers/1408.html
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Teacher
Teacher
399 Views
Registered: ‎07-09-2009
https://www.xilinx.com/support/answers/1408.html
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Visitor
Visitor
396 Views
Registered: ‎01-18-2019

Thanks! It seems I didn't search long enough :)

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