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Visitor
Visitor
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Registered: ‎12-28-2018

What's the difference about the created .bin files for a serial daisy chain?

The created .bin file of two 7series 325T apply in a serial daisy chain.
The configuration file(.bin) generated by PROMGen in ISE14.6 can config FPGA successfully  while configuration file(.bin) generated by write_CFGmem in VIVADO 2016.3 is failed.

The compare result of two .bin file is presented in following image, i do not konw the meaning of the difference and hoping somebody can explain it for me.

Configuration status register, as posted in following,indicates that the first device have released the done pin, but the second device keep done is low。

application.jpg
file_compare.jpg
first_device.jpg
second_device.jpg
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

I believe I saw your post for same issue somewhere before. Anyhow, your STAT indicates a typical DONE not released issue. To deal with daisy chain, you need to properly set the DONE status in both bitstreams. Otherwise, DONE would be held low and both FPGA would fail to start.

You do not need to look into bit because they are hard to understand. You check the bit settings. The first one should be set to float and the second one should set to pullup or drive high. 

Do not be confused by ISE or Vivado difference. Different tools, even different versions of same tool, could have different default settings. You just need to check the settings in your design.

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Visitor
Visitor
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Registered: ‎12-28-2018

thankyou your patient answer. I can not find where is the setting of done status. It seems 'drive done to high' had be canceled in vivado
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