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Visitor
Visitor
836 Views
Registered: ‎03-06-2019

Who do I rewrite the SPI configuration flash though the tandem boot PCIe port of a Virtex-7.

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I have a large PCIe board design that uses a Virtex-7 (XC7VX330TFFG1761-2) as the PCIe interface (using tandem boot),  I'd like to be able to rewrite the Virtex's SPI configuration flash by sending a new bit file from the PCIe interface to the SPI flash, but all the SPI pins are marked as prohibited in I/O planning.  How do I get around this problem and write to the flash from the PCIe interface.

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Moderator
Moderator
766 Views
Registered: ‎01-15-2008

if you are using tandem prom configuration than you will not be able to access the configuration flash from logic as persist option is enabled. check the user guide page 172/173 from the link

https://www.xilinx.com/support/documentation/ip_documentation/pcie_7x/v3_3/pg054-7series-pcie.pdf

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Adventurer
Adventurer
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Registered: ‎05-23-2018

Instantiate the Axi Quad SPI with the Option STARTUPE2. The pins (mostly CCLK, as the rest is a regular Bank) can be accessed through the STARTUPE2 primitive.

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Visitor
Visitor
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Registered: ‎03-06-2019

Do I need to disable the STARTUP primitive in the PCIe core to do this? What about the configuration Persist requirment of the Tandem PROM?  

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Moderator
Moderator
767 Views
Registered: ‎01-15-2008

if you are using tandem prom configuration than you will not be able to access the configuration flash from logic as persist option is enabled. check the user guide page 172/173 from the link

https://www.xilinx.com/support/documentation/ip_documentation/pcie_7x/v3_3/pg054-7series-pcie.pdf

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Visitor
Visitor
732 Views
Registered: ‎03-06-2019

That's what I was afraid of.  Thanks for the reply.

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