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bfung_2
Contributor
Contributor
487 Views
Registered: ‎07-02-2020

Zynq 7020 PUDC_B floating?

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I'm planning IO for a custom board and I'd like to use BANK 13 with LVCMOS25 logic level IOs.

I need to figure out what to do with the PUDC_B IO in Bank 34 (which I'm not powering as I'm not using this bank at all).

I take it without powering on Bank 34 that the IOs are useless. What are the consequences of leaving PUDC_B floating? What alternatives are there to either tie this pin high or low without powering on Bank 34?

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ddn
Xilinx Employee
Xilinx Employee
418 Views
Registered: ‎06-06-2018

Hi @bfung_2 ,

Please refer this AR#59958 which describes what happens if PUDC pin is left floating.

Regards,
Deepak D N
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ddn
Xilinx Employee
Xilinx Employee
419 Views
Registered: ‎06-06-2018

Hi @bfung_2 ,

Please refer this AR#59958 which describes what happens if PUDC pin is left floating.

Regards,
Deepak D N
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