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Mattecip_98
Newbie
Newbie
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Registered: ‎07-18-2020

Zynq ultrascale+ JTAG Debugging

Hi everyone, I'm trying to debug zynq ultrascale+  XCZU4EV-SFVC784 with boundary scan application and I found difficulties in the Interconnect test.

First of all I managed to write the jtag_ctrl register to enable the arm dap and launch the infrastructure test that passed, but I cound find a way to control the FPGA and in the interconnect test I read all zero's.

Someone can help?

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