06-05-2020 12:02 PM
hello every one
i am working with AXI DMA
i am configuring registers in vhdl using state machine
strange thing is DMA does not assert Tready signal unless i constantly write length register on every handshake(Awvalid/Wvalid). If i write only one time and stop any more transactions on axi write channel then DMA only takes in 4 beats and t ready signal is permanently low. If i constantly write length register then DMA takes in the streaming data coming from my own stream IP which is just a counter. It generates some fixed number of data beats and asserts T last signal on last one and then starts again. DMA transfers all the data in the Block ram ( for simplicity i am using a block ram). After the whole transfer is complete i read the status register and it shows me the DMA is halted and DMA internal error bit goes to high and also the IOC_irq and Err_irq bit goes to high as well. If some one can shed some light on what could be wrong here
06-10-2020 03:21 AM
This sounds like a known problem in the S2MM engine: it needs to be prevented from accepting data into the engine prior to configuration. Otherwise it will accept four data values in and you've seen the rest. So, in spite of the fact that TREADY is high, you'll need to make certain nothing transfers until the core has been configured for the transfer.
03-08-2021 07:02 AM