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Observer
Observer
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Registered: ‎03-17-2020

first xilinx fpga project (spartan-7, XC7S15 development board)

Moderators, please change to appropriate forum for this post (Other FPGA?)

Hello, I ordered from SEEED a development board which is supports two configurations: Arduino add-on, and FPGA development. The product is https://www.seeedstudio.com/Spartan-Edge-Accelerator-Board-p-4261.html 

I'm a competent HW developer, SW and Firmware developer with embedded experience, but a FPGA novice.

I'm browsing the Vivado WebPack (free) edition documentation, and also the various PDFs related to Spartan-7. Can MicroBlaze core be installed in this FPGA? Are performance metrics available, and can we have more than one MicroBlaze instances on this particular device? 

Also, could anyone share real-world current consumption data for  Spartan-7 project with a modest amount of Logical Elements? Is there a handy formula for LUT - LE calculation?

 

Regards

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Scholar
Scholar
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Registered: ‎08-07-2014

@n3rdx,

For all answers look at page5, Table-2 of this doc - https://www.xilinx.com/support/documentation/white_papers/wp501-microblaze.pdf

 

 

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978 Views
Registered: ‎07-23-2019

Yes, Spartan-7 supports Microblaze.

I'd say yes, you can have more than one (if it makes sense...). About performance metrics and space/number, what happens is it depends how you configure it, MB is quite flexible, you can have from a relatively small, simple microcontroller to a Linux-capable processor one. Synthesis can also be optimized for space or performance, so figures will vary. In short, microblaze is more a "family" of things than a single thing in that respect.

For power estimation, you can browse for the Xilinx Power estimator, it's excel-based. Also, after synthesis, in the implemented design, you have a more accurate power estimation (based on the actual logic used).

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Observer
Observer
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Registered: ‎03-17-2020

Yes, I found that document (thank you). I was wondering about Figure 5, and if I could use my first xilinx device to emulate that architecture (2-3 Microblaze) to try a triple modular redundancy controller scheme. What I am curious about is that since I do not have a Zync SOC on hand whether I could get a soft core similar to the ARM Cortex -xx to load on the Spartan-7 and begin development on the Spartan-7 ($35/board from SEEED, with a minimum of resources as possible. Then once the firmware takes shape I could shift over to Zync SoC devices..... pie in the sky dream?
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867 Views
Registered: ‎07-23-2019

The only TMR I know in Zynq is in the PMU, not in the APU or RPU cores. There are zynq boards fairly cheap, if that's your target I can't see the point in developing on a different platform. 

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Advisor
Advisor
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Registered: ‎04-26-2015

ARM apparently makes the Cortex-M1 and Cortex-M3 soft cores available for FPGAs - but keep in mind that these are very, very lightweight cores compared to what the Zynq PS offers (in much the same way that an Arduino and a Raspberry Pi are different). The FPGA fabric isn't big enough and fast enough to run a full application processor at decent speed. MicroBlaze might be a bit quicker (since it was designed for FPGAs), but it's a substantially different architecture.

 

The XC7S15 would be a great platform to develop your non-CPU code on. Need to interface to a camera or display? Get some practice with Verilog/VHDL? Investigate I/O characteristics? It'll do all of that very well. I'd do that, but then plan to move on to the Zynq before doing any significant work on the software side.

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Observer
Observer
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Registered: ‎03-17-2020

Thank you. I have made progress. I was able to define a custom board file for the Spartan Edge Accelerator (SEEED Studio) and am extracting from the schematic the connectivity and other device blocks for a wholesome Vivado 2019.2 board definition. If any one wants to use the board file for testing, let me know. If it is good enough, it could be released somehow. Just as an aside, I had the time (COVID-19) to write a mini mysql database application (barebones) that allowed me to take UG475 pin files (for any FPGA) and store the pin data into a table - and then generate the XML formatted content for the board file - I think it will save me (as a hobbyist) a lot of time in the future when I transition the design to other boards, or find another custom board (not supported by XIILINX) and that I want to use as a dev board under Vivado/VITIS. I'm only concentrating on the devices directly associated with the FPGA {oscillator, switches, jumpers, camera, etc,} for now as I can use the board in its intended #2 configuration - with the JTAG interface as the entry point. Learning a lot though in the process.
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Observer
Observer
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Registered: ‎03-17-2020

hello, can I ask for tips on indirect programming, discussed in section  Programming the SPI Flash In-System, p. 13 of  XAPP586 (v1.3) October 28, 2016 document set. I will be, as indicated, in this thread above continue defining a custom board spec for the Spartan Edge Accelerator PCB by SEEED Studio. I have traced the schematic and there is a Winbond flash device W25Q32JVZPIG connected essentially by four lines as follows to a XC7S15 FTGB196 device

 

schematic signal (flash device signal)FPGA pin destinationFPGA pin destination name
FPGA_ESP_IO5 (/CS)E13IO_L10N_T1_D15_14
FPGA_ESP_IO6 (DI, MOSI)F14IO_L9N_T1_DQS_D13_14
FPGA_ESP_IO7 (DO, MISO)F13IO_L10P_T1_D14_14
FPGA_ESP_IO8 (CLK) G14IO_L9P_T1_DQS_14

 

I would like to pose a question - in order to understand (for future custom board design) the Vivado specific process for 'indirect programming'. Here, obviously the flash device is directly connected to the FPGA device. But it is connected to (in my opinion) essentially to any pin the designer could find suitable. The four destinations seem to be grouped close to gether E, F, G rows and 13, 14 columns (per UG475 docs that is fine). But in which module do we define this connectivity? My suspicion is the board file, and I haven't yet tackled the details of <connections> and <interfaces>  sections of  the board file just yet, and only have defined a top level part0. But could somebody with Vivado architecture details kindly share their knowledge of just how does the toolchain normally determine how to define the onboard connectivity, in order  to execute the following:

"The first step to programming the SPI flash in-system requires that the 7 series FPGAs be first loaded with an interface design that bridges the programming cable to the SPI flash.  "

Or does the indirect programming process actually require the use of specific pins in Bank 0? 

Regards

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Advisor
Advisor
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Registered: ‎04-26-2015

@n3rdx If you want the FPGA to boot from the attached flash chip, it has to be connected to specific pins, because those are the only ones that the FPGA uses when attempting to configure itself. The tools will (by default) bridge the JTAG connection across to those pins. I'm not sure if the default can be changed, but even if it can be there's not often much point (because the FPGA isn't going to boot from the flash chip if it's connected to the wrong pins).

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Observer
Observer
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Registered: ‎03-17-2020


@u4223374 wrote:

@n3rdxIf you want the FPGA to boot from the attached flash chip, it has to be connected to specific pins, because those are the only ones that the FPGA uses when attempting to configure itself. The tools will (by default) bridge the JTAG connection across to those pins. 


That is what I would like to identify. Where can  I find the 'specific pins' required(doc ref.)? 

Thanks

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Registered: ‎07-23-2019

 

There is a configuration user manual for the 7 series, that should include these details.

https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

 

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Observer
Observer
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Registered: ‎03-17-2020

@archangel-lightworks I do have UG470 as you mention. If I may ask: In Table 2-2  Configuration Mode Pins (Table 1 of 2) , if I follow the column Master SPI and sub-column x1, I see that pin configuration matches Figure 2-12 x1/x2 mode. Will in-circuit programming methods also work in x2 or x4 mode if the appropriate pins were enabled, or only x1?


@archangel-lightworks wrote:

 

There is a configuration user manual for the 7 series, that should include these details.

https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

 


 

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Visitor
Visitor
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Registered: ‎06-13-2019

hallo .

could you please share the custom board file im very interested for personal use i dont know how to make the custom board files yet .

regards enri 

enri.itp@gmail.com

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Visitor
Visitor
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Registered: ‎06-13-2019

halo can you answer yes or no 

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Observer
Observer
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Registered: ‎03-17-2020

stand by .. was engaged in another project. Uploading a zip file shortly. Let me know what difficulties you face when loading this, perhaps I will need to help you with the load process, but for now, here it is (next post) ... 

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Observer
Observer
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Registered: ‎03-17-2020

@enrico I am unsure of what link to provide to download the board file repo I have created, it is a total of 1963 KB and needs to be placed in a folder, and then in Vivado 2020.x or 2019.x added in the Tools > Settings > Xhub store > Board Repository field. If you do it correctly, and then exit out to shell, and then restart Vivado (it only works at startup) you will be able to create a board specific project. If you need the process, ask me later. 

I include:

  1. Annotated schematic of the board
  2. 3D cad Step file
  3. Several directories, showing the progression of the board.xml file collection (you can expand from here)
  4. Different hardware board files for examples so you continue adding peripherals 

Please add your custom board peripherals (external peripherals) to the same board file (I added Digilent PMOD OLEGrgb etc.) to this same file, increment revision number, and then post it back to this XILINX forum thread if you would thank you.

Ask me if you get stuck. The compressed zip folder is attached here. Please add in your annotations to the PDF schematic using FoxIT PDF reader if you can. thanks.

If you could consider creating a tutorial PDF with screenshots on how you load a custom board file, with this example, that could help other XILINX developers. 

Samudra N3RDX

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Visitor
Visitor
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Registered: ‎06-13-2019

nice .

thank you so much ill get right at it .

will let you k ow later if im stuck somewhere .

i was wandering how you make the xml files for the board what app you use .

 

thanks and regards enri 

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Visitor
Visitor
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Registered: ‎06-13-2019

The files work perfectly thank you so much 

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Observer
Observer
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Registered: ‎03-17-2020


@enri30 wrote:

 

i was wandering how you make the xml files for the board what app you use .

 

thanks and regards enri 


I made these files mostly by hand, after looking at the other files, and also writing a little MySQL database application to process the pin file to extract the canonical names from Xilinx supplied FPGA files. I then built from scratch (and many attempts) the XML files for the board definition - and also had to load (many times) the Vivado program to see if the XML entries worked. If there is a single error in the XML board file, it will not load! Very annoying. If you add in any other modules (see the annotated schematic) please let me know. I also tried recently to write VITIS application for the accelerometer and was able to get basic I2C queries. But the supplied sample code from ST Microsystems was very very difficult for me to understand and then I had to read everything that Xilinx has about I2C interfacing and eventually figured it out after a lot of effort, so at the present, I am not using any of the ST Microsystems code.

Will you be using I2C in your application. Please consider sharing your experience as you do. What are you trying to do generally?

 

Also, if you want, you could accept the solution and close this forum topic.

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