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xilinxcocuk
Observer
Observer
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Registered: ‎11-06-2020

general questions to a 7series chip

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Hello,

I want to use a FPGA in my next system design. I want to use the 7series chip XC7S6-1CPGA196C. In UG475 and UG470 I found this document and have a few questions to it.

 

1. What is the "Memory Byte Group"?

2. I understand that a FPGA has multiple banks. The banks can have different voltage levels (I think). Is it possible to connect the dataoutput pins of an ADC to two different banks?

3. What is the difference between CONFIG, HR and NA?

4. Also how do I know which pins of the FPGA support LVDS?

 

Thanks!

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joancab
Mentor
Mentor
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Registered: ‎05-11-2015

1. What is the "Memory Byte Group"?

When you interface a DDR memory, the data lines can be 16, 32, 48, etc. but they come in groups of 8 and have other signals associated (strobe, etc). That is a memory byte group.

2. I understand that a FPGA has multiple banks. The banks can have different voltage levels (I think). Is it possible to connect the data output pins of an ADC to two different banks?

Yes, banks can have different voltages. In principle, no problem in connecting signals from one chip to different banks. What you need to make sure is that the protocol and voltages are compatible. You may also find certain signals, especially high speed ones, is better to keep them in the same bank, but for things like an SPI, etc. you can mix banks.

3. What is the difference between CONFIG, HR and NA?

I think you mean:

CONFIG pins: these are for configuration. You shouldn't use them for other purposes. 

HR: High Range pin, the other type is HP (high performance). The former have a wider voltage range but reduced speed range, the latter are lower voltage but faster speed.

NA: ? Probably 'not available'?

4. Also how do I know which pins of the FPGA support LVDS?

First of all, differential pins (those with XXXX_P and XXXX_N). Second, pins supporting LVDS_25, what in turn depends on Vcco of that bank. Spartan7 only has HR banks and they support LVDS provided the bank voltage is correct. 

Other useful documents to peruse are:

ds189-spartan-7-data-sheet 

ug475_7Series_Pkg_Pinout 

ug471_7Series_SelectIO 

 

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

2) An ADC is an input to the FPGA. The pins used for the ADC are dedicated pins, look at the pin out doc for the device

3) without a reference as to where they are used, NA probably means Not Applicable, HR is probably the High Range banks of the FPGA , config is probably the configuration pins you use to program the FPGA,

4) LVDS, look at the FPGA data sheet, 

 

The pin placement questions, I find its best to just make a simple dummy design and try to put the pins on the FPGA , the tools will tell you if its possible or not and give a good clue as to why.

As for 1) , give us  the reference your referring to, just the link is to general, where in the link,

post  a picture of the excerpt

 

 

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joancab
Mentor
Mentor
502 Views
Registered: ‎05-11-2015

1. What is the "Memory Byte Group"?

When you interface a DDR memory, the data lines can be 16, 32, 48, etc. but they come in groups of 8 and have other signals associated (strobe, etc). That is a memory byte group.

2. I understand that a FPGA has multiple banks. The banks can have different voltage levels (I think). Is it possible to connect the data output pins of an ADC to two different banks?

Yes, banks can have different voltages. In principle, no problem in connecting signals from one chip to different banks. What you need to make sure is that the protocol and voltages are compatible. You may also find certain signals, especially high speed ones, is better to keep them in the same bank, but for things like an SPI, etc. you can mix banks.

3. What is the difference between CONFIG, HR and NA?

I think you mean:

CONFIG pins: these are for configuration. You shouldn't use them for other purposes. 

HR: High Range pin, the other type is HP (high performance). The former have a wider voltage range but reduced speed range, the latter are lower voltage but faster speed.

NA: ? Probably 'not available'?

4. Also how do I know which pins of the FPGA support LVDS?

First of all, differential pins (those with XXXX_P and XXXX_N). Second, pins supporting LVDS_25, what in turn depends on Vcco of that bank. Spartan7 only has HR banks and they support LVDS provided the bank voltage is correct. 

Other useful documents to peruse are:

ds189-spartan-7-data-sheet 

ug475_7Series_Pkg_Pinout 

ug471_7Series_SelectIO 

 

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miker
Xilinx Employee
Xilinx Employee
488 Views
Registered: ‎11-30-2007

@xilinxcocuk 

Q1: What is the "Memory Byte Group"?

A1: That is pin grouping when targeting a memory controller (i.e. Memory Interface Solutions (UG586)).

Q2:  Is it possible to connect the data output pins of an ADC to two different banks?

A2:  In general, yes.  There are considerations for combining IOs and IO Standards in a single I/O Bank.  You can reference UG471 (v1.10) under the section Rules for Combining I/O Standards in the Same Bank.

Q3:  What is the difference between CONFIG, HR and NA?

A3:  CONFIG is the Configuration I/O Bank (I/O Bank 0 powered by VCCO_0).  HR is High Range (HR) I/O Bank.  NA is Not Applicable.

Q4:  Also how do I know which pins of the FPGA support LVDS?

A4:  In the CPGA196 package, 96 of 100 pins support LVDS (ref UG475; v1.18; Table 1-7; p 22).  A snippet from the package file can be seen below.  You are looking for the LxxP/LxxN pair.

Pin  Pin Name                      Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
A13  IO_0_14                       NA                 14    NA            NA                  HR        NA  <-- NO LVDS SUPPORT as there is no LxxP/LxxN naming pair.
C10  IO_L1P_T0_D00_MOSI_14         0                  14    NA            NA                  HR        NA  <-- LVDS SUPPORT as this is the "P" side (_L1P_) of the pair.  See below for mating pair.
C11  IO_L1N_T0_D01_DIN_14          0                  14    NA            NA                  HR        NA  <-- LVDS SUPPORT as this is the "N" side (_L1N_) of the pair.  See above for mating pair.
B11  IO_L2P_T0_D02_14              0                  14    NA            NA                  HR        NA
A12  IO_L2N_T0_D03_14              0                  14    NA            NA                  HR        NA
B10  IO_L3P_T0_DQS_PUDC_B_14       0                  14    NA            NA                  HR        NA
A10  IO_L3N_T0_DQS_EMCCLK_14       0                  14    NA            NA                  HR        NA
B9   IO_L4P_T0_D04_14              0                  14    NA            NA                  HR        NA
A9   IO_L4N_T0_D05_14              0                  14    NA            NA                  HR        NA
C12  IO_L5P_T0_D06_14              0                  14    NA            NA                  HR        NA
B12  IO_L5N_T0_D07_14              0                  14    NA            NA                  HR        NA
D13  IO_L6P_T0_FCS_B_14            0                  14    NA            NA                  HR        NA
C13  IO_L6N_T0_D08_VREF_14         0                  14    NA            NA                  HR        NA

Below is the excerpt from UG475 Table 1-12.

forums_ug475_v1_18_table1_12.png

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xilinxcocuk
Observer
Observer
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Registered: ‎11-06-2020

Thank you for your insights sir. I have a question to UG475. There are VCCO_# Pins, these pins set the voltage levels of the banks. There are also this VREF pins. V_REF_34 for example sets the input threshold voltage level for bank34. So if a voltage applied to a pin of bank 34 is >VREF then the FPGA will see it as a high signal. Is this correct?

When I use them as user I/Os which voltage will VREF then have? And how does the FPGA know if this pin is used as a user I/O or as a reference?

vref.PNG

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drjohnsmith
Teacher
Teacher
319 Views
Registered: ‎07-09-2009

Vref pins are either

 

the ADC ref pins, not used by IO pins

or

used on SOME of the many IO standards the IO can support, 

     The only one that come to my mind is the DDR memory types

     As ever

   all this is in the data sheet that are linked to by others

     I know

   there is a LOT of data to get up to speed on

    I was "luck" when I started with Xilinx 2K series, it was much simpler and has grown exponentaly.

       I would suggest that you keep the docs open and do word searches

    hopefuly we have given you some pointers,

 

Note to Xilinx, 

   any one want to write a starters guide to the different parts of the FPGA 

   

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